UM10430 Datasheet, PDF (814/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller

UM10430 NXP
Table
Bit
2:0
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code which indicates the type of the last error to occur on the CAN bus.
This field will be cleared to ‘0’ when a message has been transferred
(reception or transmission) without error. The unused code ‘111’ may be
written by the CPU to check for updates.
0x0
No error.
0x1
Stuff error: More than 5 equal bits in a sequence have occurred in a
part of a received message where this is not allowed.
0x2
Form error: A fixed format part of a received frame has the wrong
format.
0x3
AckError: The message this CAN core transmitted was not
acknowledged.
0x4
Bit1Error: During the transmission of a message (with the exception of
the arbitration field), the device wanted to send a HIGH/recessive level
(bit of logical value ‘1’), but the monitored bus value was
LOW/dominant.
0x5
Bit0Error: During the transmission of a message (or acknowledge bit,
or active error flag, or overload flag), the device wanted to send a
LOW/dominant level (data or identifier bit logical value ‘0’), but the
monitored Bus value was HIGH/recessive. During busoff recovery this
status is set each time a
sequence of 11 HIGH/recessive bits has been monitored. This enables
the CPU to monitor the proceeding of the busoff recovery sequence
(indicating the bus is not stuck at LOW/dominant or continuously
disturbed).
0x6
CRCError: The CRC checksum was incorrect in the message received.
0x7
Unused: No CAN bus event was detected (written by the CPU).
3
TXOK
Transmitted a message successfully
0
R/W
This bit is reset by the CPU. It is never reset by the CAN controller.
0
Since this bit was reset by the CPU, no message has been successfully
transmitted.
1
Since this bit was last reset by the CPU, a message has been
successfully transmitted (error free and acknowledged by at least one
other node).
4
RXOK
Received a message successfully
0
R/W
This bit is reset by the CPU. It is never reset by the CAN controller.
0
Since this bit was last reset by the CPU, no message has been
successfully transmitted.
1
Since this bit was last set to zero by the CPU, a message has been
successfully received independent of the result of acceptance filtering.
<Document ID>
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
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