UM10430 Datasheet, PDF (375/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller

UM10430 N_TBaiX_{bt l}P_{e 3}S_17Se_.ym_mdUi_eSbc_soBo_clrPn_iped_triiu_oondc_it_cpctho_ohLrmr_yoDis_{ssubetigcsiBnhacealrtsdimhpeewteiromiPetnhgeoirtsrihyoteedpriFocinrinaFhtmreoaresmitsIenmadLoseidssCxetuhRim(naPeepEsgdteRiesqtIrtoOue2eDrb0n(eIC:Fc4LLReI.PIkSNBCTDB1aE8AlixXgSxn)EetUo-dSa.edBTnd}^D_a0h^R_rbee^AH_ls^F_ecos^T_{otsD0hntRxet/eDA4}^D_Hn0FReT0t^A_{ovs0DFsiTRoct6AfeDC1FRt/5ohRvOTAD4anieDFR)sTltsTRAubrGreoAFDeiett}^TF_{lRgclTeADiosrDFRAntTRDAtecotARFDcrrTFARsoeaTFADtsler}^TlDFR_{seepTRDArARDFTFDARTRFADTADFRTFRDATADRF}
11:0 -
Reserved
-
-
31:12 PERBASE31_12 Base Address (Low)
-
R/W
These bits correspond to the memory address signals 31:12.
20.6.8 Endpoint List Address register (ENDPOINTLISTADDR - device) and
Asynchronous List Address (ASYNCLISTADDR - host) registers
20.6.8.1
Device mode
In device mode, this register contains the address of the top of the endpoint list in system
memory. Bits[10:0] of this register cannot be modified by the system software and will
always return a zero when read.The memory structure referenced by this physical
memory pointer is assumed 64 byte aligned.
Table 318. USB Endpoint List Address register in device mode (ENDPOINTLISTADDR - address 0x4000 6158) bit
description
Bit Symbol
Description
Reset Access
value
10:0 -
reserved
0
-
31:11 EPBASE31_11 Endpoint list pointer (low)
-
R/W
These bits correspond to memory address signals 31:11, respectively. This
field will reference a list of up to 4 Queue Heads (QH). (i.e. one queue head
per endpoint and direction.)
20.6.8.2
Host mode
This 32-bit register contains the address of the next asynchronous queue head to be
executed by the host. Bits [4:0] of this register cannot be modified by the system software
and will always return a zero when read.
Table 319. USB Asynchronous List Address register in host mode (ASYNCLISTADDR- address 0x4000 6158) bit
description
Bit Symbol
Description
Reset Access
value
4:0 -
Reserved
0
-
31:5 ASYBASE31_5 Link pointer (Low) LPL
-
R/W
These bits correspond to memory address signals 31:5, respectively. This
field may only reference a Queue Head (OH).
20.6.9 TT Control register (TTCTRL)
20.6.9.1 Device mode
This register is not used in device mode.
<Document ID>
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
375 of 1164