UM10430 Datasheet, PDF (981/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller

NXP Semiconductors
Table 928. Clock sources for output stages
Output stages (d = default clock source)
Clock sources
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ENET_TX_CLK no no -
GP_CLKIN
no no -
Crystal oscillator no no -
PLL0 (USB0) no d -
PLL1
no no -
IDIVA
no no -
IDIVB
no no -
IDIVC
no no -
IDIVD
no no -
IDIVE
no no -
yes yes yes -
yes yes yes -
yes yes yes -
no no no -
yes yes yes -
yes yes yes -
yes yes yes -
yes yes yes -
yes yes yes -
yes yes yes -
yes yes yes yes yes -
yes yes yes yes yes -
yes yes yes yes yes -
no no no no no -
yes yes yes yes yes -
yes yes yes yes yes -
yes yes yes yes yes -
yes yes yes yes yes -
yes yes yes yes yes -
yes yes yes yes yes -
yes yes yes yes yes yes yes yes
yes yes yes yes yes yes yes yes
yes yes yes yes yes yes yes yes
no no no no no no no yes
yes yes yes yes yes yes yes yes
yes yes yes yes yes yes yes yes
yes yes yes yes yes yes yes yes
yes yes yes yes yes yes yes yes
yes yes yes yes yes yes yes yes
yes yes yes yes yes yes yes yes
CGU
Oscillators,
clock inputs
RTCX1
RTCX2
XTAL1
XTAL2
ENET_RX_CLK
ENET_TX_CLK
GP_CLKIN
12 MHz IRC
32 kHz OSC
CRYSTAL OSC
PLLs
PLL0
PLL1
Integer
dividers
Output
generators
BASE_SAFE_CLK
BASE_USB0_CLK
IDIVA /4
IDIVB /16
IDIVC /16
IDIVD /16
IDIVE /256
5
OUTCLK_20
CLKOUT
18
OUTCLK_2 - 19
(BASE_xxx_CLK)
Fig 152. CGU block diagram
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User manual
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Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
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