UM10430 Datasheet, PDF (55/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller

UM10430 N_7TICNRa.RaX_bC4mElP_TeGeRR20S_M9e.em_gRii_esc_gto_iseRRAn_tOc/erWd_{cr d}u_eosvc_eset_sro_vc00Aoir_exxs_{fdrwf00sdi00:per40CettsoisnofingCDIRuheCrisapcttrcirioiompnntfririoegegnugirsiastettierornsr(ebgaisCsteehraa3dp2dterkeHrsz7s:o0sLxcP4ill0Ca0t1o48r3xo0xu0t0pC)uot}^Dn_a^Rf_n^Ai_dgFTuB^Dr_{ORaDAtDiFRoTAnDFTRRADe0RFRgTxADe0iDFRss0TRAet0AteFDF}^TFR_{vrTsaADFDlFR2(uTRDACBeARFDCRTFARTEFADTDFRGTRDA)ARDFTFDARTRFADTADFRTFRDATADRF}
control register.
PMUCON
0x008 Power mode control register.
0x0000 0000
-
-
0x008 - Reserved
-
0x0FC
M3MEMMAP R/W
0x100 ARM Cortex-M3 memory mapping
-
-
0x104 Reserved
-
CREG1
RO
0x108 Chip configuration register 1
CREG2
RO
0x10C Chip configuration register 2
CREG3
RO
0x110 Chip configuration register 3
CREG4
RO
0x114 Chip configuration register 4
CREG5
R/W
0x118 Chip configuration register 5. Controls JTAG access.
DMAMUX
R/W
0x11C DMA muxing control
-
-
0x120 - Reserved
-
0x124
ETBCFG
R/W
0x128 ETB RAM configuration
0x0000 0000
CREG6
R/W
0x12C
-
-
0x130 - Reserved
-
0x1FC
CHIPID
RO
0x200 Part ID
-
-
0x204 - Reserved
-
0x2FC
-
-
0x300
0x304
0x308
-
-
0x30C - Reserved
-
0xEFC
LOCKREG
0xF00 Lock register; blocks write access to CREG registers
7.4.1 IRC trim register
Table 30. IRC trim register (IRCTRM, address 0x4004 3000) bit description
Bit Symbol Description
11:0 TRM
IRC trim value
Reset
value
0x2BC
19:12 -
31:20 -
Reserved
Reserved
0xFF
-
Access
R
R
-
<Document ID>
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
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