UM10430 Datasheet, PDF (1055/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller

UM10430 NXP
Semiconductors
Table 980.
Name
DIR0
-
MASK0
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PIN0
R/W 0x014 GPIO port 0 pin value register using MASK0.
0x0
SET0
R/W 0x018 GPIO port 0 output set register using MASK0.
0x0
This register controls the state of output pins. Only
bits enabled by 0 in MASK0 can be altered.
CLR0
W
0x01C GPIO port 0 output clear register using MASK0. 0x0
This register controls the state of output pins. Only
bits enabled by 0 in MASK0 can be altered.
DIR1
R/W 0x020 GPIO port 1 direction control register.
0x0
-
-
0x024 to Reserved.
-
0x02C
MASK1
R/W 0x030 GPIO port 1 mask register for port access.
0x0
PIN1
R/W 0x034 GPIO port 1 pin value register using MASK1.
0x0
SET1
R/W 0x038 GPIO port 1 output set register using MASK1.
0x0
This register controls the state of output pins. Only
bits enabled by 0 in MASK1 can be altered.
CLR1
W
0x03C GPIO port 1 output clear register using MASK1. 0x0
This register controls the state of output pins. Only
bits enabled by 0 in MASK1 can be altered.
DIR2
R/W 0x040 GPIO port 2 direction control register.
0x0
-
-
0x044 to Reserved.
-
0x04C
MASK2
R/W 0x050 GPIO port 2 mask register for port access.
0x0
PIN2
R/W 0x054 GPIO port 2 pin value register using MASK2.
0x0
SET2
R/W 0x058 GPIO port 2 output set register using MASK2.
0x0
This register controls the state of output pins. Only
bits enabled by 0 in MASK2 can be altered.
CLR2
W
0x05C GPIO port 2 output clear register using MASK2. 0x0
This register controls the state of output pins. Only
bits enabled by 0 in MASK2 can be altered.
DIR3
R/W 0x060 GPIO port 3 direction control register.
0x0
-
-
0x064 to Reserved.
-
0x06C
MASK3
R/W 0x070 GPIO port 3 mask register for port access.
0x0
PIN3
R/W 0x074 GPIO port 3 pin value register using MASK3.
0x0
SET3
R/W 0x078 GPIO port 3 output set register using MASK3.
0x0
This register controls the state of output pins. Only
bits enabled by 0 in MASK3 can be altered.
CLR3
W
0x07C GPIO port 3 output clear register using
0x0
FIO3MASK. This register controls the state of
output pins. Only bits enabled by 0 in MASK3 can
be altered.
DIR4
R/W 0x080 GPIO port 4 direction control register.
0x0
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User manual
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Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
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