UM10430 Datasheet, PDF (972/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller

UM10430 NXP
Semiconductors
42.3.4.2 CREG0 control
Table 917. CREG0
Bit Symbol
0
EN1KHZ
register
register (CREG0, address 0x4004 3004)
Value Description
Enable 1 kHz output
0
1 kHz output disabled
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1
1 kHz output enabled
1
EN32KHZ
Enable 32 kHz output
0
R/W
0
32 kHz output disabled
1
32 kHz output enabled
2
RESET32KHZ
32 kHz oscillator reset
1
R/W
0
<tbd>
1
<tbd>
3
32KHZPD
32 kHz power control
1
R/W
0
32 kHz oscillator powered
1
32 kHz oscillator powered-down
7:4 -
Reserved
-
-
9:8 BODLVL1
BOD trip level to generate an interrupt: 11
R/W
0x0
2.75 V
0x1
2.85 V
0x2
2.95 V
0x3
3.05 V
11:10 BODLVL2
BOD trip level to generate a reset:
11
R/W
0x0
1.70 V
0x1
1.80 V
0x2
1.90 V
0x3
2.00 V
31:12 -
Reserved
-
-
42.3.4.3 Power mode control register
For details on power mode selection, see Section 8.2.
Table 918. Power mode control register (PMUCON, address 0x4004 3008) bit description
Bit Symbol
Value Description
Reset Access
value
1:0 PMUCON
Controls power mode:
0
R/W
0x0
Normal
0x1
Low-power
0x2
Reserved
0x3
Normal
31:2 -
Reserved
-
-
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User manual
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Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
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