UM10430 Datasheet, PDF (536/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller

UM10430 NXP
Semiconductors
Table
Bit
10
11
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12 LE
Length Error
When set, this bit indicates that the actual length of the frame received and
that the Length/ Type field does not match. This bit is valid only when the
Frame Type (RDES0[5]) bit is reset.
13 SAF
Source Address Filter Fail
When set, this bit indicates that the SA field of frame failed the SA Filter in the
MAC Core.
14 DE
Descriptor Error
When set, this bit indicates a frame truncation caused by a frame that does not
fit within the current descriptor buffers, and that the DMA does not own the
Next Descriptor. The frame is truncated. This field is valid only when the Last
Descriptor (RDES0[8]) is set.
15 ES
ES: Error Summary
Indicates the logical OR of the following bits:
• RDES0[1]: CRC Error
• RDES0[3]: Receive Error
• RDES0[4]: Watchdog Timeout
• RDES0[6]: Late Collision
• RDES0[7]: Giant Frame
• RDES4[4:3]: IP Header/Payload Error
• RDES0[11]: Overflow Error
• RDES0[14]: Descriptor Error
This field is valid only when the Last Descriptor (RDES0[8]) is set.
29:16 FL
Frame Length
These bits indicate the byte length of the received frame that was transferred
to host memory (including CRC). This field is valid when Last Descriptor
(RDES0[8]) is set and either the Descriptor Error (RDES0[14]) or Overflow
Error bits are reset. The frame length also includes the two bytes appended to
the Ethernet frame when IP checksum calculation (Type 1) is enabled and the
received frame is not a MAC control frame. This field is valid when Last
Descriptor (RDES0[8]) is set. When the Last Descriptor and Error Summary
bits are not set, this field indicates the accumulated number of bytes that have
been transferred for the current frame.
30 AFM
Destination Address Filter Fail
When set, this bit indicates a frame that failed in the DA Filter in the MAC
Core.
31 OWN
Own Bit
When set, this bit indicates that the descriptor is owned by the DMA of the
MAC Subsystem. When this bit is reset, this bit indicates that the descriptor is
owned by the Host. The DMA clears this bit either when it completes the frame
reception or when the buffers that are associated with this descriptor are full.
<Document ID>
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
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