UM10430 Datasheet, PDF (1107/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller

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In Basic mode the evaluation of all Message Object related control and status bits and of
the control bits of the IFx Command Mask Registers is turned off. The message number of
the Command request registers is not evaluated. The NEWDAT and MSGLST bits of the
IF2 Message Control Register retain their function, DLC3-0 will show the received DLC,
the other control bits will be read as ‘0’.
In Basic mode the ready output CAN_WAIT_B is disabled (always ‘1’)
Software control of pin CAN_TXD: Four output functions are available for the CAN
transmit pin CAN_TXD:
1. serial data output (default).
2. drives CAN sample point signal to monitor the CAN controller’s timing.
3. drives recessive constant value.
4. drives dominant constant value.
The last two functions, combined with the readable CAN receive pin CAN_RXD, can be
used to check the CAN bus’ physical layer.
The output mode of pin CAN_TXD is selected by programming the Test Register bits TX1
and TX0 as described Section 42.10.6.1.6.
Remark: The three test functions for pin CAN_TXD interfere with all CAN protocol
functions. The CAN_TXD pin must be left in its default function when CAN message
transfer or any of the test modes Loo-back mode, Silent mode, or Basic mode are
selected.
42.10.7.3 CAN message handler
The Message handler controls the data transfer between the Rx/Tx Shift Register of the
CAN Core, the Message RAM and the IFx Registers, see Figure 171.
The message handler controls the following functions:
• Data Transfer between IFx Registers and the Message RAM
• Data Transfer from Shift Register to the Message RAM
• Data Transfer from Message RAM to Shift Register
• Data Transfer from Shift Register to the Acceptance Filtering unit
• Scanning of Message RAM for a matching Message Object
• Handling of TXRQST flags
• Handling of interrupts
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User manual
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Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
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