UM10430 Datasheet, PDF (283/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller

UM10430 NXP Sem₁i₆c_.o₇n_.1d_.6uct_ATdo_{eh••H}r_aes_{BlStLiDhnopegmMcliktDwAa,eMirstdCehtAtoetrarynraCl,tlniroatnosynnlftpltedeererorresslfcClraeforoohocrfnraresAtsaptrHaeoitnlesuBlssprrctota1rweann6onsad:esnALwasdPHcafdCtrBiitoeos1mmsn8utsxiansn,xstlaiaintlteGvictorheleuneisnnd.otetieIrnffrargaeafna:laspcPcaeehucsrtris.ippot}^D_Ehron^R_{eeasAacrceFamah}^T_lnD.^D_{ApMcReHoADrABFfm}^R_oTA(rmpDGFml^TR_{eaPsADtseDFRtaTe.ADMrsDFRApTRi}^A_slAFD)it^TF_{cRcToaADorpDFRnTRa}^DA_{retARFDbrtTFARloreTFyADlT,lDFRoeTRDAfrARDFTFDARTRFADTADFRTFRDATADRF}
• Setting of protection bits for transfers on each stream.
16.7.1.6.1
Bus and transfer widths
The physical width of the AHB bus is 32 bits. Source and destination transfers can be of
differing widths and can be the same width or narrower than the physical bus width. The
DMA Controller packs or unpacks data as appropriate.
16.7.1.6.2 Endian behavior
The DMA Controller can cope with both little-endian and big-endian addressing. Software
can set the endianness of each AHB master individually.
Internally the DMA Controller treats all data as a stream of bytes instead of 16-bit or 32-bit
quantities. This means that when performing mixed-endian activity, where the endianness
of the source and destination are different, byte swapping of the data within the 32-bit data
bus is observed.
Note: If byte swapping is not required, then use of different endianness between the
source and destination addresses must be avoided. Table 217 shows endian behavior for
different source and destination combinations.
Table 217. Endian behavior
Source
endian
Destination Source
endian
width
Little
Little
8
Little
Little
8
Little
Little
8
Little
Little
16
Destination
width
8
16
32
8
Source
Source data Destination Destination data
transfer
transfer
no/byte lane
no/byte lane
1/[7:0]
21
1/[7:0]
21212121
2/[15:8]
43
2/[15:8]
43434343
3/[23:16]
65
3/[23:16]
65656565
4/[31:24]
87
4/[31:24]
87878787
1/[7:0]
21
1/[15:0]
43214321
2/[15:8]
43
2/[31:16]
87658765
3/[23:16]
65
4/[31:24]
87
1/[7:0]
21
1/[31:0]
87654321
2/[15:8]
43
3/[23:16]
65
4/[31:24]
87
1/[7:0]
21
1/[7:0]
21212121
1/[15:8]
43
2/[15:8]
43434343
2/[23:16]
65
3/[23:16]
65656565
2/[31:24]
87
4/[31:24]
87878787
<Document ID>
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
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