UM10430 Datasheet, PDF (1005/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller

NXP Semiconductors
42.5.2 Basic configuration
The CCU1/2 are configured as follows:
• See Table 951 for clocking and power control.
• Do not reset the CCUs during normal operation.
Table 951. CCU clocking and power control
Base clock
Branch clock
CCU1
BASE_M3_CLK
CLK_M3_BUS
CCU2
BASE_M3_CLK
CLK_M3_BUS
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Maximum frequency
150 MHz
150 MHz
42.5.3 Features
The CCUs switch the clocks to individual peripherals on or off.
• Auto mode activates the AHB disable protocol before switching off the branch clock.
• Wake-up mode allows to select clocks to run automatically after a wake-up event.
42.5.4 General description
Each CGU base clock has several clock branches which can be turned on or off
independently by the Clock Control Units CCU1 or CCU2. The branch clocks are
distributed between CCU1 and CCU2.
Table 952. CCU1 branch clocks
Base clock
Branch clock
BASE_APB3_CLK CLK_APB3_BUS
CLK_APB3_I2C1
CLK_APB3_DAC
CLK_APB3_ADC0
CLK_APB3_ADC1
CLK_APB3_CAN
BASE_APB1_CLK CLK_APB1_BUS
CLK_APB1_MOTOCON
CLK_APB1_I2C0
CLK_APB1_I2S
BASE_SPIFI_CLK CLK_SPIFI
Description
Clock to the I2C1 register interface and I2C1
peripheral clock.
Clock to the DAC register interface.
Clock to the ADC0 register interface and ADC0
peripheral clock.
Clock to the ADC1 register interface and ADC1
peripheral clock.
Clock to the C_CAN register interface and
C_CAN peripheral clock.
Clock to the PWM Motor control block and PWM
Motocon peripheral clock.
Clock to the I2C0 register interface and I2C0
peripheral clock.
Clock to the I2S register interface and I2S
peripheral clock.
clock for the SPIFI SCKI clock input.
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Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
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