UM10430 Datasheet, PDF (438/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller

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containing digital circuitry to provide USB2.0 On-The-Go functionality.
USB2.0 provides plug-and-play connection of peripheral devices to a host with three
different data speeds: High-Speed with a data rate of 480 Mbps, Full-Speed with a data
rate of 12 Mbps, Low-Speed with a data rate of 1.5 Mbps. Many portable devices can
benefit from the ability to communicate to each other over the USB interface without
intervention of a host PC. The addition of the On-The-Go functionality to USB makes this
possible without losing the benefits of the standard USB protocol.
Support of the High-Speed data rate and the OTG functionality requires an external USB
HS OTG PHY that connects to the USB controller via the ULPI interface. Full-Speed or
Low-Speed is supported through the on-chip Full-speed PHY.
21.5 Pin description
Table 359. USB1 pin description
Function name
Direction
USB1_DP
I/O
USB1_DM
I/O
USB1_VBUS
I
USB1_VBUS_EN
O
USB1_IND0
O
USB1_IND1
O
USB1_PWR_FAULT I
ULPI pins
ULPI_DATA[7:0]
I/O
ULPI_STP
O
ULPI_NXT
I
ULPI_DIR
I
ULPI_CLK
I
Description
USB1 bidirectional D+ line.
USB1 bidirectional D line.
VBUS pin (power on USB cable).
VBUS power enable.
Port indicator LED control output 0.
Port indicator LED control output 1.
Port power fault signal indicating over-current condition;
this signal monitors over-current on the USB bus (external
circuitry required to detect over-current condition).
ULPI link 8-bit bidirectional data bus timed on the rising
clock edge.
ULPI link STP signal. Asserted to end or interrupt transfers
to the PHY.
ULPI link NXT signal. Data flow control signal from the
PHY.
ULPI link DIR signal. Controls the DATA bus direction.
ULPI link CLK signal. 60 MHz clock generated by the PHY.
<Document ID>
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
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