UM10430 Datasheet, PDF (669/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller

UM10430 NXP Semiconductors
27.5 Pin description
Table 573.
Pin name
QEI_A
QEI_B
QEI pin
I/O
I
I
Chapter 27: LPC18xx
description
Description
Used as the Phase A (PhA) input
Used as the Phase B (PhB) input
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QEI_IDX I
Used as the Index (IDX) input to the Quadrature Encoder Interface.
27.6 Register description
Table 574. Register overview: QEI (base address 0x400C 6000)
Name
Access Address Description
offset
Control registers
CON
WO
0x000
Control register
STAT
RO
0x004
Encoder status register
CONF
R/W
0x008
Configuration register
Position, index, and timer registers
POS
RO
0x00C Position register
MAXPOS
R/W
0x010
Maximum position register
CMPOS0
R/W
0x014
position compare register 0
CMPOS1
R/W
0x018
position compare register 1
CMPOS2
R/W
0x01C position compare register 2
INXCNT
RO
0x020
Index count register
INXCMP0
R/W
0x024
Index compare register 0
LOAD
R/W
0x028
Velocity timer reload register
TIME
RO
0x02C Velocity timer register
VEL
RO
0x030
Velocity counter register
CAP
RO
0x034
Velocity capture register
VELCOMP
R/W
0x038
Velocity compare register
FILTERPHA R/W
0x03C
Digital filter register on input phase
A (QEI_A)
FILTERPHB R/W
0x040
Digital filter register on input phase
B (QEI_B)
FILTERINX R/W
0x044
Digital filter register on input index
(QEI_IDX)
WINDOW
R/W
0x048
Index acceptance window register
INXCMP1
R/W
0x04C Index compare register 1
INXCMP2
R/W
0x050
Index compare register 2
Interrupt registers
IEC
WO
0xFD8 Interrupt enable clear register
IES
WO
0xFDC Interrupt enable set register
INTSTAT
RO
0xFE0 Interrupt status register
Reset value
0
0
0x000F 0000
0
0
0xFFFF FFFF
0xFFFF FFFF
0xFFFF FFFF
0
0xFFFF FFFF
0xFFFF FFFF
0xFFFF FFFF
0
0xFFFF FFFF
0
0
0
0
0x0000 0000
0xFFFF FFFF
0xFFFF FFFF
0
0
0
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User manual
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Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
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