UM10430 Datasheet, PDF (1011/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller

UM10430 NXP Semiconductors
Table 955. Register overview:
Name
CLK_APB2_USART3_STAT
-
CLK_APB2_USART2_CFG
CCU2 (base
Access
R
-
R/W
address 0x4005 2000)
Address Description
offset
0x204 CLK_APB2_UART3
0x208 to Reserved
0x2FC
0x300 CLK_APB2_UART2
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CLK_APB2_USART2_STAT
R
0x304 CLK_APB2_UART2 status register
0x0000 0001
-
-
0x308 to Reserved
-
0x3FC
CLK_APB0_UART1_CFG
R/W
0x400 CLK_APB0_UART1 configuration register 0x0000 0001
CLK_APB0_UART1_STAT
R
0x404 CLK_APB0_UART1 status register
0x0000 0001
-
-
0x408 to Reserved
-
0x4FC
CLK_APB0_USART0_CFG
R/W
0x500 CLK_APB0_UART0 configuration register 0x0000 0001
CLK_APB0_USART0_STAT
R
0x504 CLK_APB0_UART0 status register
0x0000 0001
-
-
0x508 to Reserved
-
0x5FC
CLK_APB2_SSP1_CFG
R/W
0x600 CLK_APB2_SSP1 configuration register 0x0000 0001
CLK_APB2_SSP1_STAT
R
0x604 CLK_APB2_SSP1 status register
0x0000 0001
-
-
0x608 to Reserved
-
0x6FC
CLK_APB0_SSP0_CFG
R/W
0x700 CLK_APB0_SSP0 configuration register 0x0000 0001
CLK_APB0_SSP0_STAT
R
0x704 CLK_APB0_SSP0 status register
0x0000 0001
-
-
0x708 to Reserved
-
0x7FC
CLK_SDIO_CFG
R/W
0x800 CLK_SDIO configuration register
0x0000 0001
CLK_SDIO_STAT
R
0x804 CLK_SDIO status register
0x0000 0001
42.5.5.1
Power mode register
This register contains a single bit, PD, that when set will disable all output clocks with
Wake-up enabled (i.e. W = 1 in the CCU branch clock configuration registers,
Section 42.5.5.3). Clocks disabled by writing to this register will be reactivated when a
wake-up interrupt is detected or when a 0 is written into the PD bit.
Table 956. CCU1/2 power mode register (CCU1_PM, address 0x4005 1000 and CCU2_PM,
address 0x4005 2000) bit description
Bit Symbol Value Description
Reset Access
value
0
PD
Initiate power-down mode
0
R/W
0
Normal operation.
1
Clocks with wake-up mode enabled (W = 1) are
disabled.
31:1 -
Reserved.
-
-
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User manual
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
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