UM10430 Datasheet, PDF (976/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller

UM10430 NXP
Semiconductors
Table 921. DMA muxing
Bit Symbol
31:30 DMAMUXCH15
register
Value
0x0
0x1
(_sIDDDD_{2eMAeMSlesC1A}A_cctcMr_{psihepUDartXiniMpon},_hnAea_eld_rt1oad_lr_p1e_e5s_r:s_iph0_ex_r4_a0_l0_c4_o^D_n^R3_n^A1_e1^F_c^TC_t^D)_io^Rb_n^ADi^Ct_f^FR_od^ThA_re^aDFs^TRpc^ADtr^eFRi^Tp^rAD_Rv0t^D_a^FR4_ei^ToR_l^A2_suAn^FD_e^:_e^TFR_t^AT…^ADpD_RA^FRc^TRDAp_c/o_WARFDn_c^eTFAtR_eⁿi_Tn^FAD_s^du^TDFR_se^iTRDAxd_{ARDFTFDARTRFADTADFRTFRDATADRF}
0x2 Reserved
0x3 Reserved
42.3.4.7
ETB SRAM configuration register
This register selects the interface that is used to the 16 kB block of RAM located at
address 0x2000 C000. This RAM memory block can be accessed either by the ETB or be
used as normal SRAM on the AHB bus.
Note that by default, this memory area will be accessed by the ETB.
Table 922. ETB SRAM configuration register (ETBCFG, address 0x4004 3128) bit description
Bit Symbol Value Description
0
ETB
31:1 -
Select SRAM interface
0
ETB accesses SRAM at address 0x2000 C000.
1
AHB accesses SRAM at address 0x2000 C000.
Reserved.
Reset
value
0
Access
R/W
-
-
42.3.4.8 CREG6 control register
This register controls various aspects of the LPC18xx:
• Bits 2:0 control the Ethernet PHY interface. The ethernet block reads this register
during set-up, and therefore the ethernet must be reset after changing the PHY
interface.
• Bits 5:4 control the input channel 7 of the combined timer inputs (see Figure 178).
Input channel 7 is connected to input 7 of the SCT and the CAP2 channel of timer 3.
• Bits 8:6 control the input mux to the timer capture channels CAP1 and CAP2 and the
SCT (see Figure 178). These particular capture inputs can be either routed to the
timer input pins or are connected to the USART receive/transmit wait signal in smart
card mode.
<Document ID>
User manual
Table 923. CREG6 control register (CREG6, address 0x4004 312C) bit description
Bit Symbol
Value Description
Reset Access
value
2:0 ETHMODE
Selects the Ethernet mode. Reset the ethernet
R/W
after changing the PHY interface.
All other settings are reserved.
0x0 MII
0x4 RMII
3-
USB0 ATX override. Selects USB0 RPU usage.
R/W
Reserved.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
976 of 1164