UM10430 Datasheet, PDF (475/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller

UM10430 NXP
Table
Bit
16
3^S9_TS8^e_Xy.^m_mSUbⁱS^c_oBl^oEⁿn^dd^up_01Voa^c_li^t_un^o_et ^r0^sCo_{EETSDnxonnetrfddset}o_wppcnl_ooradri_iire_ppnneog_tttiicosio_ns_atkntat_n.e_sllr_etwad(_lrE_litN_e D_aP_oT_nC_eT_toR_tL_h0_is-_b^Ca_itd^h_td^a_or^pe_fo^ts^e_rs_c^r_e0²x_t¹_h4_e^:0^L0_e0^P_nd^C7_p¹1_o⁸C_in^x0_t ^x)_t^D_ob^RU_ri^At_e^SF_td^T_u^Be_r^D1_ns^Rc_a^HADr^Fi^Rop^TAst^D_Rv^Fi^to^TR_a^/_en^DA_l^D_su^FeR_ee…^TADv_t^DFRc^icToRAn^eAFDt^TFRi_RA^cn_TADu^o_/cDFRWe_c^nTRd^DA_e^tARFDr_s^TFARo_{sTFADlTlDFReTRDArARDFTFDARTRFADTADFRTFRDATADRF}
STALL handshake to the Host. It will continue returning STALL until
the bit is cleared by software, or it will automatically be cleared upon
receipt of a new SETUP request.
After receiving a SETUP request, this bit will continue to be cleared
by hardware until the associated ENDSETUPSTAT bit is cleared.^[1]
17 -
-
Reserved
19:18 TXT
0x0
Endpoint type
0
RO
Endpoint 0 is always a control endpoint.
22:20 -
-
Reserved
23 TXE
1
Tx endpoint enable
1
RO
Endpoint enabled. Control endpoint 0 is always enabled. This bit is
always 1.
31:24 -
-
Reserved
[1] There is a slight delay (50 clocks max) between the ENPTSETUPSTAT being cleared and hardware continuing to clear this bit. In most
systems it is unlikely that the DCD software will observe this delay. However, should the DCD notice that the stall bit is not set after
writing a one to it, software should continually write this stall bit until it is set or until a new setup has been received by checking the
associated ENDPTSETUPSTAT bit.
21.6.23 Endpoint 1 to 3 control registers
Each endpoint that is not a control endpoint has its own register to set the endpoint type
and enable or disable the endpoint.
Remark: The reset value for all endpoint types is the control endpoint. If one endpoint
direction is enabled and the paired endpoint of opposite direction is disabled, then the
endpoint type of the unused direction must be changed from the control type to any other
type (e.g. bulk). Leaving an unconfigured endpoint control will cause undefined behavior
for the data PID tracking on the active endpoint.
Table 399. USB Endpoint 1 to 3 control registers (ENDPTCTRL - address 0x4000 71C4 (ENDPTCTRL1) to
0x4000 71CC (ENDPTCTRL3)) bit description
Bit Symbol Value Description
Reset
value
Access
0
RXS
Rx endpoint stall
0
R/W
0
Endpoint ok.
This bit will be cleared automatically upon receipt of a SETUP
request if this Endpoint is configured as a Control Endpoint and this
bit will continue to be cleared by hardware until the associated
ENDPTSETUPSTAT bit is cleared.
1
Endpoint stalled
Software can write a one to this bit to force the endpoint to return a
STALL handshake to the Host. It will continue returning STALL until
the bit is cleared by software, or it will automatically be cleared upon
receipt of a new SETUP request.^[1]
<Document ID>
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
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