UM10430 Datasheet, PDF (269/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller

UM10430 NXP
Semiconductors
Table
Bit
7:0
197. DMA
Symbol
INTSTAT
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1 - the corresponding channel does have an active interrupt
request.
31:8 -
Reserved. Read undefined.
-
-
16.6.2 DMA Interrupt Terminal Count Request Status Register
The INTTCSTAT Register is read-only and indicates the status of the terminal count after
masking.
Table 198. DMA Interrupt Terminal Count Request Status Register (INTTCSTAT, address
0x4000 2004) bit description
Bit Symbol
Description
7:0 INTTCSTAT Terminal count interrupt request status for DMA
channels. Each bit represents one channel:
0 - the corresponding channel has no active terminal
count interrupt request.
1 - the corresponding channel does have an active
terminal count interrupt request.
Reset
value
0x00
Access
RO
31:8 -
Reserved. Read undefined.
-
-
16.6.3 DMA Interrupt Terminal Count Request Clear Register
The INTTCCLEAR Register is write-only and clears one or more terminal count interrupt
requests. When writing to this register, each data bit that is set HIGH causes the
corresponding bit in the status register (IntTCStat) to be cleared. Data bits that are LOW
have no effect.
Table 199. DMA Interrupt Terminal Count Request Clear Register (INTTCCLEAR, address
0x4000 2008) bit description
Bit Symbol
Description
Reset Access
value
7:0 INTTCCLEAR Allows clearing the Terminal count interrupt request 0x00 WO
(IntTCStat) for DMA channels. Each bit represents one
channel:
0 - writing 0 has no effect.
1 - clears the corresponding channel terminal count
interrupt.
31:8 -
Reserved. Read undefined. Write reserved bits as
-
-
zero.
16.6.4 DMA Interrupt Error Status Register
The INTERRSTAT Register is read-only and indicates the status of the error request after
masking.
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User manual
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Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
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