UM10430 Datasheet, PDF (206/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller

UM10430 NXP
Semiconductors
Table
Bit
2:0
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0x2
Function 2
0x3
Function 3
0x4
Function 4
0x5
Function 5
0x6
Function 6
0x7
Function 7
3
EPD
Enable pull-down resistor at pad
0
R/W
0
Disable pull-down.
1
Enable pull-down.
4
EPUN
Disable pull-up resistor at pad. By default, 0
R/W
the pull-up resistor is enabled at reset.
0
Enable pull-up
1
Disable pull-up
5
EHS
Slew rate
0
R/W
0
Slow
1
Fast
6
EZI
Input buffer enable. The input buffer is
0
R/W
disabled by default at reset but must be
enabled to transfer data from the I/O buffer to
the pad.
0
Disable input buffer
1
Enable input buffer
7
-
Reserved
-
-
9:8 EHD
Select drive strength
0
R/W
0x0
Standard drive: 4 mA drive strength
0x1
Medium drive: 8 mA drive strength
0x2
High drive: 14 mA drive strength
0x3
Ultra-high drive: 20 mA drive strength
31:10 -
Reserved
-
-
13.4.3 ADC0 function select register
For pins which have digital and analog functions, this register selects the input channel of
the ADC0 over any of the possible digital functions. This option is not available for channel
ADC0_7.
In addition, each analog function is pinned out on a dedicated analog pin which is not
affected by this register.
The following pins are controlled by the ENAIO0 register:
<Document ID>
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
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