UM10430 Datasheet, PDF (1084/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller

UM10430 NXP
Semiconductors
Table 1015.Register overview:
Name
Access
-
IF2_CMDREQ
IF2_CMDMSK
C_00Ao00__{xxxxfdCf0000sdA8478er4CC0}Net _s0-s(basMDRMe _eeeeas_sssd_ecssd_raarrviggep_eeest_{disoiinnn0ttee}x_rr4_ffaa0_cc0^D_eeE^R₂₂^A2^F0_cc^T_oo0^D_mm0^R)_mm^ADCF_aa^RTh_nn^A_dd^aDFTRp_rm^A_e^Dt_a^e_q^FRT_su^rAD_ke^DFR4_s^TRA2_{tAFD:TFRAT00-Rv}^AD_xxa^pDFR_e00l^TRDAp_su00ARFDe^e_e00^TFAR_tⁿ_{10TFADdTDFRiTRDAxARDFTFDARTRFADTADFRTFRDATADRF}
IF2_MSK1
0x088
Message interface 2 mask 1
0xFFFF
IF2_MSK2
0x08C
Message interface 2 mask 2
0xFFFF
IF2_ARB1
0x090
Message interface 2 arbitration 1
0x0000
IF2_ARB2
0x094
Message interface 2 arbitration 2
0x0000
IF2_MCTRL
0x098
Message interface 2 message control 0x0000
IF2_DA1
0x09C
Message interface 2 data A1
0x0000
IF2_DA2
0x0A0
Message interface 2 data A2
0x0000
IF2_DB1
0x0A4
Message interface 2 data B1
0x0000
IF2_DB2
0x0A8
Message interface 2 data B2
0x0000
-
-
0x0AC -
0x0FC
TXREQ1
RO
0x100
Transmission request 1
0x0000
TXREQ2
RO
0x104
Transmission request 2
0x0000
-
-
0x108 -
Reserved
-
0x11C
ND1
RO
0x120
New data 1
0x0000
ND2
RO
0x124
New data 2
0x0000
-
-
0x128 -
Reserved
-
0x13C
IR1
RO
0x140
Interrupt pending 1
0x0000
IR2
RO
0x144
Interrupt pending 2
0x0000
-
-
0x148 -
Reserved
-
0x15C
MSGV1
RO
0x160
Message valid 1
0x0000
MSGV2
RO
0x164
Message valid 2
0x0000
-
-
0x168 -
Reserved
-
0x17C
CLKDIV
R/W
0x180
CAN clock divider register
0x0001
42.10.6.1 CAN protocol registers
42.10.6.1.1
CAN control register
After a hardware reset, the registers of the C_CAN controller hold the values described in
Table 904. Additionally, the busoff state is set, and the TD0/1 outputs are set to HIGH. The
reset value 0x0001 of the CANCTRL register enables initialization by software (INIT = 1).
The C_CAN does not influence the CAN bus until the CPU resets the INIT bit to 0.
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User manual
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Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
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