UM10430 Datasheet, PDF (249/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller

UM10430 NXP
Semiconductors
Table 168. Register overview: GPIO
Name
Access Address
offset
PORT_POL3 R/W 0x02C
PORT_POL4 R/W 0x030
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PORT_POL5 R/W 0x034
GPIO grouped interrupt port 5 polarity register 0xFFFF
FFFF
PORT_POL6 R/W 0x038
GPIO grouped interrupt port 6 polarity register 0xFFFF
FFFF
PORT_POL7 R/W 0x03C
GPIO grouped interrupt port 7 polarity register 0xFFFF
FFFF
PORT_ENA0 R/W 0x040
GPIO grouped interrupt port 0 enable register 0
PORT_ENA1 R/W 0x044
GPIO grouped interrupt port 1 enable register 0
PORT_ENA2 R/W 0x048
GPIO grouped interrupt port 2 enable register 0
PORT_ENA3 R/W 0x04C
GPIO grouped interrupt port 3 enable register 0
PORT_ENA4 R/W 0x050
GPIO grouped interrupt port 4 enable register 0
PORT_ENA5 R/W 0x054
GPIO grouped interrupt port 5 enable register 0
PORT_ENA6 R/W 0x058
GPIO grouped interrupt port 5 enable register 0
PORT_ENA7 R/W 0x05C
GPIO grouped interrupt port 5 enable register 0
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User manual
Table 169. Register overview: GPIO GROUP1 interrupt (base address 0x4008 9000)
Name
CTRL
Access Address
offset
R/W 0x000
Description
GPIO grouped interrupt control register
Reset
value
0
PORT_POL0 R/W 0x020
GPIO grouped interrupt port 0 polarity register 0xFFFF
FFFF
PORT_POL1 R/W
PORT_POL2 R/W
PORT_POL3 R/W
0x024
0x028
0x02C
GPIO grouped interrupt port 1 polarity register
GPIO grouped interrupt port 2 polarity register
GPIO grouped interrupt port 3 polarity register
0xFFFF
FFFF
0xFFFF
FFFF
0xFFFF
FFFF
PORT_POL4 R/W 0x030
GPIO grouped interrupt port 4 polarity register 0xFFFF
FFFF
PORT_POL5 R/W 0x034
GPIO grouped interrupt port 5 polarity register 0xFFFF
FFFF
PORT_POL6 R/W
PORT_POL7 R/W
0x038
0x03C
GPIO grouped interrupt port 6 polarity register
GPIO grouped interrupt port 7 polarity register
0xFFFF
FFFF
0xFFFF
FFFF
PORT_ENA0 R/W 0x040
GPIO grouped interrupt port 0 enable register 0
PORT_ENA1 R/W 0x044
GPIO grouped interrupt port 1 enable register 0
PORT_ENA2 R/W 0x048
GPIO grouped interrupt port 2 enable register 0
PORT_ENA3 R/W 0x04C
GPIO grouped interrupt port 3 enable register 0
PORT_ENA4 R/W 0x050
GPIO grouped interrupt port 4 enable register 0
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
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