UM10430 Datasheet, PDF (330/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller

UM10430 NXP
Semiconductors
Table
Bit
1
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self-refresh mode.
1
CLKOUT runs continuously (POR reset value).
2
SR
Self-refresh request, EMCSREFREQ. By writing 1 to this bit
1
self-refresh can be entered under software control. Writing 0 to
this bit returns the EMC to normal mode.
The self-refresh acknowledge bit in the Status register must be
polled to discover the current operating mode of the EMC.^[2]
0
Normal mode.
1
Enter self-refresh mode (POR reset value).
4:3 -
-
Reserved, user software should not write ones to reserved bits. -
The value read from a reserved bit is not defined.
5
MMC
Memory clock control.
0
0
CLKOUT enabled (POR reset value).
1
CLKOUT disabled.^[3]
6
-
-
Reserved, user software should not write ones to reserved bits. -
The value read from a reserved bit is not defined.
8:7 I
SDRAM initialization.
00
0x0 Issue SDRAM NORMAL operation command (POR reset value).
0x1 Issue SDRAM MODE command.
0x2 Issue SDRAM PALL (precharge all) command.
0x3 Issue SDRAM NOP (no operation) command)
12:9 -
-
Reserved, user software should not write ones to reserved bits. -
The value read from a reserved bit is not defined.
13
DP
Low-power SDRAM deep-sleep mode.
0
0
Normal operation (POR reset value).
1
Enter Deep-sleep mode.
31:14 -
-
Reserved, user software should not write ones to reserved bits. -
The value read from a reserved bit is not defined.
[1] Clock enable must be HIGH during SDRAM initialization.
[2] The memory controller exits from power-on reset with the self-refresh bit HIGH. To enter normal functional
mode set this bit LOW.
[3] Disabling CLKOUT can be performed if there are no SDRAM memory transactions. When enabled this bit
can be used in conjunction with the dynamic memory clock control (CS) field.
Remark: Deep-sleep mode can be entered by setting the deep-sleep mode (DP) bit, the
dynamic memory clock enable bit (CE), and the dynamic clock control bit (CS) to one. The
device is then put into a low-power mode where the device is powered down and no
longer refreshed. All data in the memory is lost.
<Document ID>
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
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