UM10430 Datasheet, PDF (383/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller

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This bit is 0 if PP (Port Power bit) is 0,
0
No change.
1
Port enabled/disabled status has changed.
4
OCA
Over-current active
0
RO
This bit will automatically transition from 1 to 0 when the over-current
condition is removed.
0
The port does not have an over-current condition.
1
The port has currently an over-current condition.
5
OCC
Over-current change
0
R/WC
This bit gets set to one when there is a change to Over-current Active.
Software clears this bit by writing a one to this bit position.
6
FPR
Force port resume
0
R/W
Software sets this bit to one to drive resume signaling. The Host Controller
sets this bit to one if a J-to-K transition is detected while the port is in the
Suspend state. When this bit transitions to a one because a J-to-K
transition is detected, the Port Change Detect bit in the USBSTS register is
also set to one. This bit will automatically change to zero after the resume
sequence is complete. This behavior is different from EHCI where the host
controller driver is required to set this bit to a zero after the resume duration
is timed in the driver.
Note that when the Host controller owns the port, the resume sequence
follows the defined sequence documented in the USB Specification
Revision 2.0. The resume signaling (Full-speed K) is driven on the port as
long as this bit remains a one. This bit will remain a one until the port has
switched to the high-speed idle. Writing a zero has no affect because the
port controller will time the resume operation clear the bit the port control
state switches to HS or FS idle.
This bit is 0 if PP (Port Power bit) is 0.
0
No resume (K-state) detected/driven on port.
1
Resume detected/driven on port.
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User manual
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
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