English
Language : 

UM10430 Datasheet, PDF (754/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller
UM10430 NXP
Table
Bit
4
6S9LS9Mey:mmSUbiAoclRoTn1dMuoVcdaetloumerCsoLTtrmDeeonheascoetsterripkncoimvibgrnleiao.gpRrcd.SteskeiIeontgmaMrpniitsaeuoltlo.tdedoTperapihn(StbaMe,eaRCf4lcrekoXRmcmDtm.o-1odtah,dedehemdatrprsieanrnosnpovssuimdte0sefxift(set4Cec0arTt0imSos8n,ec2Dcol0ohSn1oanR0pne),bicsbRatmeicItkdadtonaienndpstdeecDrrronCfiouDpaDrtRlCtlpmi)yAouhaFtntdoaTrpieapDsingdteRe,nirAsDiToraFcRsXTl3oAtiDni3DnFcnTRp1:leAuoDLicstFoRPtTopADehCfbDdFRetaTR1AlhdcAFD8ekTFiRxnTADxDFRUTRDA0RvARFDAaTFAReRTlFADsuTDFTReeTRDtA1ARDFTFDARTRFADTADFRTFRDATADRF
externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4
modem outputs are connected to the 4 modem inputs. As a result of these
connections, the upper 4 bits of the U1MSR will be driven by the lower 4 bits of the
U1MCR rather than the 4 modem inputs in normal mode. This permits modem status
interrupts to be generated in loopback mode by writing the lower 4 bits of U1MCR.
0
Disable modem loopback mode.
1
Enable modem loopback mode.
5
-
Reserved, user software should not write ones to reserved bits. The value read from a 0
reserved bit is not defined.
6
RTSEN
RTS enable.
0
0
Disable auto-rts flow control.
1
Enable auto-rts flow control.
7
CTSEN
CTS enable.
0
0
Disable auto-cts flow control.
1
Enable auto-cts flow control.
31:8 -
Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
33.5.9
Auto-flow control
If auto-RTS mode is enabled the UART1‘s receiver FIFO hardware controls the RTS1
output of the UART1. If the auto-CTS mode is enabled the UART1‘s U1TSR hardware will
only start transmitting if the CTS1 input signal is asserted.
33.5.9.1
Auto-RTS
The auto-RTS function is enabled by setting the RTSen bit. Auto-RTS data flow control
originates in the U1RBR module and is linked to the programmed receiver FIFO trigger
level. If auto-RTS is enabled, the data-flow is controlled as follows:
When the receiver FIFO level reaches the programmed trigger level, RTS1 is de-asserted
(to a high value). It is possible that the sending UART sends an additional byte after the
trigger level is reached (assuming the sending UART has another byte to send) because it
might not recognize the de-assertion of RTS1 until after it has begun sending the
additional byte. RTS1 is automatically reasserted (to a low value) once the receiver FIFO
has reached the previous trigger level. The re-assertion of RTS1 signals to the sending
UART to continue transmitting data.
If Auto-RTS mode is disabled, the RTSen bit controls the RTS1 output of the UART1. If
Auto-RTS mode is enabled, hardware controls the RTS1 output, and the actual value of
RTS1 will be copied in the RTS Control bit of the UART1. As long as Auto-RTS is enabled,
the value of the RTS Control bit is read-only for software.
<Document ID>
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
754 of 1164