UM10430 Datasheet, PDF (866/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller

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S
SLAVE ADDRESS RW=0
A
DATA
A
DATA
A/A
P
n bytes data transmitted
from Master to Slave
from Slave to Master
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
P = STOP condition
Fig 132. Format in the Master Transmitter mode
37.8.2
Master Receiver mode
In the master receiver mode, data is received from a slave transmitter. The transfer is
initiated in the same way as in the master transmitter mode. When the START condition
has been transmitted, the interrupt service routine must load the slave address and the
data direction bit to the I²C Data register (DAT), and then clear the SI bit. In this case, the
data direction bit (R/W) should be 1 to indicate a read.
When the slave address and data direction bit have been transmitted and an
acknowledge bit has been received, the SI bit is set, and the Status Register will show the
status code. For master mode, the possible status codes are 0x40, 0x48, or 0x38. For
slave mode, the possible status codes are 0x68, 0x78, or 0xB0. For details, refer to
Table 819.
S
SLAVE ADDRESS RW=1
A
DATA
A
DATA
A
P
n bytes data received
from Master to Slave
from Slave to Master
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
P = STOP condition
Fig 133. Format of Master Receiver mode
After a Repeated START condition, I²C may switch to the master transmitter mode.
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User manual
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Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
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