UM10430 Datasheet, PDF (343/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller

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Table 289. Static Memory Output Enable delay registers (STATICWAITOEN, address
0x4000 5208 (STATICWAITOEN0), 0x4000 5228 (STATICWAITOEN1), 0x4000 5248
(STATICWAITOEN2), 0x4000 5268 (STATICWAITOEN3)) bit description
Bit Symbol Description
Reset
value
3:0 WAITOEN Wait output enable.
0x0
Delay from chip select assertion to output enable.
0x0 = No delay (POR reset value).
0x1 - 0xF = n cycle delay. The delay is WAITOEN x tCCLK.
31:4 -
Reserved, user software should not write ones to reserved bits. The -
value read from a reserved bit is not defined.
19.7.24 Static Memory Read Delay registers
The StaticWaitRd registers enable you to program the delay from the chip select to the
read access. It is recommended that these registers are modified during system
initialization, or when there are no current or outstanding transactions. This can be
ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode. It
is not used if the extended wait bit is enabled in the StaticConfig registers. These registers
are accessed with one wait state.
Table 290. Static Memory Read Delay registers (STATICWAITRD, address 0x4000 520C
(STATICWAITRD0), 0x4000 522C (STATICWAITRD1), 0x4000 524C
(STATICWAITRD2), 0x4000 526C (STATICWAITRD3)) bit description
Bit Symbol Description
Reset
value
4:0 WAITRD Non-page mode read wait states or asynchronous page mode read first 0xB
access wait state.
[1]
Non-page mode read or asynchronous page mode read, first read only:
0x0 - 0x1E = (n + 1) CCLK cycles for read accesses. For
non-sequential reads, the wait state time is (WAITRD + 1) x tCCLK.
0x1F = 32 CCLK cycles for read accesses (POR reset value).
31:5 -
Reserved, user software should not write ones to reserved bits. The -
value read from a reserved bit is not defined.
[1] The reset value is 0x0B for the STATICWAITRD0 register only.
19.7.25 Static Memory Page Mode Read Delay registers
The StaticWaitPage registers enable you to program the delay for asynchronous page
mode sequential accesses. It is recommended that these registers are modified during
system initialization, or when there are no current or outstanding transactions. This can be
ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode.
This register is accessed with one wait state.
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Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
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