UM10430 Datasheet, PDF (907/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller

UM10430 NXP
39.5
Semiconductors
Register description
Table 836. Register
Name
CR
overview:
Access
R/W
DAC (base
Address
offset
0x000
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CTRL
R/W
0x004
DAC control register.
0
CNTVAL
R/W
0x008
DAC counter value register.
0
39.5.1 D/A converter register
This read/write register includes the digital value to be converted to an analog output
value and a bit that trades off performance vs. power.
Table 837: D/A Converter register (CR - address 0x400E 1000) bit description
Bit Symbol Value Description
5:0 -
15:6 VALUE
16 BIAS
0
1
31:17 -
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
After the selected settling time after this field is written with a
new VALUE, the voltage on the DACOUT pin (with respect to
V_SSA) is VALUE/1024  VDDA.
Settling time
The settling time of the DAC is 1 s max, and the maximum
current is 700 A.
The settling time of the DAC is 2.5 s and the maximum
current is 350 A.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Reset
value
-
0
0
-
39.5.2 D/A Converter Control register
This read/write register enables the DMA operation and controls the DMA timer.
Table 838. D/A Control register (CTRL - address 0x400E 1004) bit description
Bit Symbol
Value Description
Reset
value
0
INT_DMA_REQ
DMA request
0
0
This bit is cleared on any write to the DACR register.
1
This bit is set by hardware when the timer times out.
1
DBLBUF_ENA
DMA double-buffering
0
0
DACR double-buffering is disabled.
1
When this bit and the CNT_ENA bit are both set, the
double-buffering feature in the DACR register will be
enabled. Writes to the DACR register are written to a
pre-buffer and then transferred to the DACR on the next
time-out of the counter.
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User manual
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
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