UM10430 Datasheet, PDF (349/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller

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Note: The static memory can be accessed as normal when the SDRAM memory is in
self-refresh mode.
19.9.1 Low-power SDRAM Deep-sleep Mode
The EMC supports JEDEC low-power SDRAM deep-sleep mode. Deep-sleep mode can
be entered by setting the deep-sleep mode (DP) bit, the dynamic memory clock enable bit
(CE), and the dynamic clock control bit (CS) in the DynamicControl register. The device is
then put into a low-power mode where the device is powered down and no longer
refreshed. All data in the memory is lost.
19.9.2 Low-power SDRAM partial array refresh
The EMC supports JEDEC low-power SDRAM partial array refresh. Partial array refresh
can be programmed by initializing the SDRAM memory device appropriately. When the
memory device is put into self-refresh mode only the memory banks specified are
refreshed. The memory banks that are not refreshed lose their data contents.
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User manual
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
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