UM10430 Datasheet, PDF (132/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller

UM10430 NXP
Semiconductors
Table
Bit
0
1
101. Reset external
description
Symbol
-
CORE_RESET
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0 = Reset not activated
1 = Reset activated
31:2
-
Reserved. Do not modify; read as logic 0.
0
-
11.4.4.3 Reset external status register 2 for MASTER_RST
Table 102. Reset external status register 2 (RESET_EXT_STAT2, address 0x4005 3408) bit
description
Bit Symbol
1:0 -
Description
Reserved. Do not modify; read as logic 0.
Reset
value
0
Access
-
2
PERIPHERAL_RESET Reset activated by PERIPHERAL_RST
0
R/W
output. Write 0 to clear.
0 = Reset not activated
1 = Reset activated
31:3 -
Reserved. Do not modify; read as logic 0.
0
-
11.4.4.4 Reset external status register 4 for WWDT_RST
Table 103. Reset external status register 4 (RESET_EXT_STAT4, address 0x4005 3410) bit
description
Bit Symbol
Description
Reset Access
value
0
-
Reserved. Do not modify; read as logic 0.
0
-
1
CORE_RESET
Reset activated by CORE_RST output. Write 0
R/W
0 to clear.
0 = Reset not activated
1 = Reset activated
31:2 -
Reserved. Do not modify; read as logic 0.
0
-
11.4.4.5 Reset external status register 5 for CREG_RST
Table 104. Reset external status register 5 (RESET_EXT_STAT5, address 0x4005 3414) bit
description
Bit Symbol
Description
Reset Access
value
0
-
Reserved. Do not modify; read as logic 0.
0
-
1
CORE_RESET
Reset activated by CORE_RST output. Write 0
R/W
0 to clear.
0 = Reset not activated
1 = Reset activated
31:2 -
Reserved. Do not modify; read as logic 0.
0
-
<Document ID>
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
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