UM10430 Datasheet, PDF (685/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller

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the counter and compare register.
CTRL
R/W
0x008
Control register.
0xC
COUNTER
R/W
0x00C
32-bit counter
0
[1] Reset Value reflects the data stored in used bits only. It does not include content of reserved bits.
28.5.1 RI Compare Value register
Table 607. RI Compare Value register (COMPVAL - address 0x400C 0000) bit description
Bit Symbol Description
31:0 RICOMP Compare register. Holds the compare value which is
compared to the counter.
Reset value
0xFFFF FFFF
28.5.2 RI Mask register
Table 608. RI Mask register (MASK - address 0x400C 0004) bit description
Bit Symbol Description
Reset
value
31:0 RIMASK
Mask register. This register holds the 32-bit mask value. A one written 0
to any bit overrides the result of the comparison for the corresponding
bit of the counter and compare register (causes the comparison of the
register bits to be always true).
28.5.3 RI Control register
Table 609. RI Control register (CTRL - address 0x400C 0008) bit description
Bit Symbol Value Description
Reset
value
0
RITINT
Interrupt flag
0
1
This bit is set to 1 by hardware whenever the counter value
equals the masked compare value specified by the contents
of RICOMPVAL and RIMASK registers.
Writing a 1 to this bit will clear it to 0. Writing a 0 has no
effect.
0
The counter value does not equal the masked compare
value.
1
RITENCLR
Timer enable clear
1
The timer will be cleared to 0 whenever the counter value 0
equals the masked compare value specified by the contents
of RICOMPVAL and RIMASK registers. This will occur on
the same clock that sets the interrupt flag.
0
The timer will not be cleared to 0.
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User manual
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Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
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