UM10430 Datasheet, PDF (953/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller

UM10430 NXP
Table
Bit
28
29
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30 IAB_SPIFI
SPIFI interrupt active.
0
Read: 0 indicates that the interrupt is not active, 1 indicates that the interrupt is active.
31: -
Reserved.
0
30
42.1.8.6 Interrupt Priority Register 0
The IPR0 register controls the priority of the first 4 peripheral interrupts. Each interrupt can
have one of 32 priorities, where 0 is the highest priority.
Table 892. Interrupt Priority Register 0 (IPR0 - address 0xE000 E400) bit description
Bit Symbol
Description
Reset
value
2:0 -
Reserved. These bits ignore writes, and read as 0.
0
7:3 IP_DAC
DAC interrupt priority. 0 = highest priority. 31 (0x1F) = lowest 0
priority.
10:8 -
Reserved.These bits ignore writes, and read as 0.
0
15:11 IP_ER
Event router interrupt priority. 0 = highest priority. 31 (0x1F) = 0
lowest priority.
18:16 -
These bits ignore writes, and read as 0.
0
23:19 IP_DMA
DMA interrupt priority. 0 = highest priority. 31 (0x1F) = lowest 0
priority.
26:24 -
Reserved.These bits ignore writes, and read as 0.
0
31:27 -
Reserved.
-
42.1.8.7 Interrupt Priority Register 1
The IPR1 register controls the priority of the second group of 4 peripheral interrupts. Each
interrupt can have one of 32 priorities, where 0 is the highest priority.
Table 893. Interrupt Priority Register 1 (IPR1 - address 0xE000 E404) bit
description
Bit Symbol Description
2:0 -
Reserved.These bits ignore writes, and read as 0.
7:3 -
Reserved.
10:8 -
Reserved.These bits ignore writes, and read as 0.
15:11 IP_ETHER ETHERNET interrupt priority. 0 = highest priority. 31 (0x1F) = lowest
NET
priority.
18:16 -
Reserved.These bits ignore writes, and read as 0.
Reset
value
0
0
0
0
0
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User manual
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Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
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