UM10430 Datasheet, PDF (340/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller

UM10430 NXP Sem1i9c.o7n.2d0uctTtseTDhoynhheysrseetsnurseeDreamelyemrdnveinaabgiimcntyiisatitwMcldeiRzayresainattmiasaniomCrgneoai,ucrasonyc0mrtc:ilwR3eetmhshrAeseeogeSnrEdiystC.Mh&twIehetCirratCiseshpisAeraoteneirnSdcearelobe1nDmwl,9oeaeam:cynilLtueoadPsrnuyrttCdeahteonr1teedet8np.oxgtrehroxinaosgEtturetaxtetrhsmtirneteasgsDrtnnheRldoeaAriwFlneRTMgg-ApDitesRorStmaAwDenFaRroeTssnArraD,FdayTRcorCtACeDrioFRAodmTnADSinsDsFRotaTR.AldrabATFDoitfTFlRhleieTelADinedsdDFRcrTRDAmcid(eARFDaEuoTsFARnrMTdFADifnbTeoDFRCgeT.RDrA)ARDFTFDARTRFADTADFRTFRDATADRF
Note: The values programmed into these registers must be consistent with the values
used to initialize the SDRAM memory device.
Table 286. Dynamic Memory RASCAS Delay registers (DYNAMICRASCAS, address
0x4000 5104 (DYNAMICRASCAS0), 0x4000 5124 (DYNAMICRASCAS1),
0x4000 5144 (DYNAMICRASCAS2), 0x4000 5164 (DYNAMICRASCAS3)) bit
description
Bit Symbol Value Description
Reset
value
1:0 RAS
RAS latency (active to read/write delay).
11
7:2 -
9:8 CAS
0x0 Reserved.
0x1 One CCLK cycle.
0x2 Two CCLK cycles.
0x3 Three CCLK cycles (POR reset value).
-
Reserved, user software should not write ones to reserved bits. -
The value read from a reserved bit is not defined.
CAS latency.
11
31:10 -
0x0 Reserved.
0x1 One CCLK cycle.
0x2 Two CCLK cycles.
0x3 Three CCLK cycles (POR reset value).
-
Reserved, user software should not write ones to reserved bits. -
The value read from a reserved bit is not defined.
19.7.21 Static Memory Configuration registers
The StaticConfig registers configure the static memory configuration. It is recommended
that these registers are modified during system initialization, or when there are no current
or outstanding transactions. This can be ensured by waiting until the EMC is idle, and then
entering low-power, or disabled mode. These registers are accessed with one wait state.
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Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
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