UM10430 Datasheet, PDF (1014/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller

UM10430 NXP
Semiconductors
Table
Bit
0
959._{RSy1CU1mCN0bU0o1, l0bxr4a0nV010ca5hl1uc1el0o4c,k.RCCD..c,ulleoo}o0_nsccnxc_kkef4ri_{niiig0sspa0utbed5irolni}a_se1antaiA_bo_bl0len_e0ddr)_.e_{.bgiitsdteersc(CriLpKti_o}^DXn^RX^AX^F_^TC^DF^RAG^DCFR,^Tha^AaDd^FTRpd^AD_1Rvr^tee^FR_ae^Ts^rAD_lsus^DFR4_eee^TRA2_tsAFD:TFR0^ATADx_RA^pDFR4^TRDA0^p_/cWAR0^FD_c^eTFA5^R_e^nTF_{sADdTDsFRiTRDAxARDFTFDARTRFADTADFRTFRDATADRF}
1
AUTO
Auto (AHB disable mechanism) enable
0
R/W
0
Auto is disabled.
1
Auto is enabled.
2
WAKEUP
Wake-up mechanism enable
0
R/W
0
Wake-up is disabled.
1
Wake-up is enabled.
31:3
-
Reserved
-
-
Table 960. CCU2 branch clock configuration register (CLK_XXX_CFG, addresses 0x4005
2100, 0x4005 2200,..., 0x4005 2800) bit description
Bit
Symbol Value Description
Reset Access
value
0
RUN
Run enable
1
R/W
0
Clock is disabled.
1
Clock is enabled.
1
AUTO
Auto (AHB disable mechanism) enable
0
R/W
0
Auto is disabled.
1
Auto is enabled.
2
WAKEUP
Wake-up mechanism enable
0
R/W
0
Wake-up is disabled.
1
Wake-up is enabled.
31:3
-
Reserved
-
-
42.5.5.4
CCU1/2 branch clock status registers
Like the Configuration Register, each generated output clock from the CCU has a status
register. When the configuration register of an output clock is written into, the value of the
actual hardware signals may not be updated immediately because of the Auto or Wake-up
mechanism. The Status Register shows the current value of these signals. All output clock
Status Registers follow the format as described in Table 961 and Table 962.
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User manual
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Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
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