UM10430 Datasheet, PDF (471/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller

UM10430 NXP
Table
Bit
4
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1
Disabled.
Setting to a 1 ensures that overruns/underruns of the latency FIFO are
eliminated for low bandwidth systems where the RX and TX buffers are
sufficient to contain the entire packet. Enabling stream disable also has the
effect of ensuring the the TX latency is filled to capacity before the packet is
launched onto the USB.
Note: Time duration to pre-fill the FIFO becomes significant when stream
disable is active. See TXFILLTUNING to characterize the adjustments
needed for the scheduler when using this feature.
5
VBPS
VBUS power select
0
R/WO
31:6 -
0
vbus_pwr_select is set LOW.
1
vbus_pwr_select is set HIGH
-
Reserved
-
-
21.6.17 USB Endpoint Setup Status register (ENDPSETUPSTAT)
Table 393. USB Endpoint Setup Status register (ENDPTSETUPSTAT - address 0x4000 71AC) bit description
Bit Symbol Description
Reset
value
Access
3:0 ENDPT
SETUP
STAT
Setup endpoint status for logical endpoints.
0
For every setup transaction that is received, a corresponding bit in this register
is set to one. Software must clear or acknowledge the setup transfer by writing
a one to a respective bit after it has read the setup data from Queue head. The
response to a setup packet as in the order of operations and total response
time is crucial to limit bus time outs while the setup lockout mechanism is
engaged.
R/WC
31:4 -
Reserved
-
-
21.6.18 USB Endpoint Prime register (ENDPTPRIME)
For each endpoint, software should write a one to the corresponding bit whenever posting
a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin
parsing for a new transfer descriptor from the queue head and prepare a receive buffer.
Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.
Remark: These bits will be momentarily set by hardware during hardware endpoint
re-priming operations when a dTD is retired and the dQH is updated.
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User manual
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
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