UM10430 Datasheet, PDF (774/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller

UM10430 NXP
Semiconductors
Table
Bit
0
71_{LS7By:MmbSbiSot} PldeCsV₀₁ocanrliutpreotiloR_LDSDnoe_eueog_rrsiipai_ncslgrBti_ie_npanr_ptcoiu1_kormtnM(_iC_saolR_tdao1_ekpe.-_enra_afd_rtiod_omr_ne_.s_ths_e0_sx_e4_r0_ia0_l 8_ou3_t0^D_p0^CR_u4_t^Ah₍^F(_M^aS^Tp_OS^DtRP_S^eAD0_I^rFR)_o,^T3A_r0^4DF_Mx^:TR_I4^AL_S^D0^FR_O^P0^TADC^C₎^DFR_r^T1RA_a5_A8FDt0_h^TFRx0_eTAD4^x_rDFR(^STRDAS_0RvARFDSSa^TF_e^ARPPl_Ts^FA_u^D1^0T_eDFRe)^/_tTRDA)^{1ARDFTFDARTRFADTADFRTFRDATADRF}
than the serial input pin (MISO or MOSI respectively).
1
SSE
SSP Enable.
0
0
The SSP controller is disabled.
1
The SSP controller will interact with other devices on the serial
bus. Software should write the appropriate control information to
the other SSP registers and interrupt controller registers, before
setting this bit.
2
MS
Master/Slave Mode.This bit can only be written when the SSE bit 0
is 0.
0
The SSP controller acts as a master on the bus, driving the
SCLK, MOSI, and SSEL lines and receiving the MISO line.
1
The SSP controller acts as a slave on the bus, driving MISO line
and receiving SCLK, MOSI, and SSEL lines.
3
SOD
Slave Output Disable. This bit is relevant only in slave mode
0
(MS = 1). If it is 1, this blocks this SSP controller from driving the
transmit data line (MISO).
31:4 -
Reserved, user software should not write ones to reserved bits. NA
The value read from a reserved bit is not defined.
34.6.3 SSP Data Register
Software can write data to be transmitted to this register, and read data that has been
received.
Table 718: SSP Data Register (DR - address 0x4008 3008 (SSP0), 0x400C 5008 (SSP1)) bit
description
Bit Symbol Description
Reset
value
15:0 DATA
Write: software can write data to be sent in a future frame to this
register whenever the TNF bit in the Status register is 1, indicating that
the Tx FIFO is not full. If the Tx FIFO was previously empty and the
SSP controller is not busy on the bus, transmission of the data will
begin immediately. Otherwise the data written to this register will be
sent as soon as all previous data has been sent (and received). If the
data length is less than 16 bits, software must right-justify the data
written to this register.
0x0000
Read: software can read data from this register whenever the RNE bit
in the Status register is 1, indicating that the Rx FIFO is not empty.
When software reads this register, the SSP controller returns data from
the least recent frame in the Rx FIFO. If the data length is less than 16
bits, the data is right-justified in this field with higher order bits filled with
0s.
31:16 -
Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
<Document ID>
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
774 of 1164