UM10430 Datasheet, PDF (472/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller

UM10430 N_TB3a:iX_{0bt l}P_{e 3}S_9PS4e_Ey.m_mRUBbi_Sc_oBlo_En_nd_du_pPFbOwDuoorc_heUifrimesft_nTeenco_etraertrr_Pibcevaps_{rhenentirdimsOpopparneUeoocpitTsrnieoattiegnnrren.giesddScatpefeoooinrfvritenwe(aEwta,bNrrauteerDfcacfseePonhirrsTvorffePeeousRrrlodpdppIoMwehensyrErdaicstiter-iniciopagaantdlobodOfriContrtUreieohswTsatasoshepneet0ntthenexdtenop4radco012pUoi0n1borS0tryi:sneB.Lst7s.ohp1PHfooBtCawsn0rt1da)dii8rnnwbexigitatitxa}^D_orbdet^RU_ieret^A_ewssSFqical^TB_ulre^D_{Ui1psRSttHADiBaoFRonTAsDF0RvtTR/aeDADlsuFeReeTADvtDFRicTRAeAFDTFRcRATADoc/DFRWncTRDAetSARFDrsTFARosTFADlTlDFReTRDArARDFTFDARTRFADTADFRTFRDATADRF}
automatically use this bit to begin parsing for a new transfer descriptor from the
queue head and prepare a receive buffer. Hardware will clear this bit when the
associated endpoint(s) is (are) successfully primed.
PERB0 = endpoint 0
...
PERB3 = endpoint 3
15:4 -
Reserved
-
-
19:16 PETB
Prime endpoint transmit buffer for physical IN endpoints.
0
R/WS
For each IN endpoint a corresponding bit is set to one by software to request a
buffer be prepared for a transmit operation in order to respond to a USB
IN/INTERRUPT transaction. Software should write a one to the corresponding
bit when posting a new transfer descriptor to an endpoint. Hardware will
automatically use this bit to begin parsing for a new transfer descriptor from the
queue head and prepare a transmit buffer. Hardware will clear this bit when the
associated endpoint(s) is (are) successfully primed.
PETB0 = endpoint 0
...
PETB3 = endpoint 3
31:20 -
Reserved
-
-
21.6.19 USB Endpoint Flush register (ENDPTFLUSH)
Writing a one to a bit(s) in this register will cause the associated endpoint(s) to clear any
primed buffers. If a packet is in progress for one of the associated endpoints, then that
transfer will continue until completion. Hardware will clear this register after the endpoint
flush operation is successful.
Table 395. USB Endpoint Flush register (ENDPTFLUSH - address 0x4000 71B4) bit description
Bit Symbol Description
Reset
value
3:0 FERB
Flush endpoint receive buffer for physical OUT endpoints.
0
Writing a one to a bit(s) will clear any primed buffers.
FERB0 = endpoint 0
...
FERB3 = endpoint 3
Access
R/WS
<Document ID>
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
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