UM10430 Datasheet, PDF (506/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller

UM10430 NXP
Table
Bit
6
7
4^S29_RRS^e.y_IU^m_EmDEⁱ_bM^c_oA^o_l ⁿIn^dt_RRDWRe^u_eeeer_hr_cscc^c_eu_eeecn^tp_iiirvvv^oti_teeephe^r_tiibI^sn_sinnoua_tbtnefeb_fitrerl_rre_iruusuppr_se_ntteg_aeisti_vns_waeat_iinbe_tlahalr_ebbN(_lD_leeoM_drem.nA_Waa__blI_hN_IleenT_nte__trE_hruiN_sp,_tba_Sitd_uid_smr_re_mes_sas_erty0_, x_ER4_ne0_ac0_be1_liev1_e(0_bI1_nitC_te1)_r6rb_uii_npt _t^Cd_t^D_hie_s^Rh_iss^Aa_dc^F_ri^p_esr^Ti^t_agp^De_bist^Rr_li_te^Ao^D_e²_d^Fn^R_r²_.)^TA_,^:D…^FLTRc^APDo^FRn^C_0Rv0^Tt^ADi_a¹n_e^DFR_lu⁸_s^TRA_ue^x_eAFDed_t^TxFRTADEDFR_RRA^tTRDA_c//^h_WWARFDc^eTFAR_e^rTFAD_s^nTDFR_s^{eTRDAtARDFTFDARTRFADTADFRTFRDATADRF}
When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register),
Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive
Buffer Unavailable Interrupt is disabled.
8
RSE
Received stopped enable
0
R/W
When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register),
Receive Stopped Interrupt is enabled. When this bit is reset, Receive Stopped
Interrupt is disabled.
9
RWE
Receive watchdog timeout enable
0
R/W
When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register),
the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, Receive
Watchdog Timeout Interrupt is disabled.
10
ETE
Early transmit interrupt enable
0
R/W
When this bit is set with an Abnormal Interrupt Summary Enable (bit 15 in this
register), Early Transmit Interrupt is enabled. When this bit is reset, Early Transmit
Interrupt is disabled.
12:11 -
Reserved
0
RO
13
FBE
Fatal bus error enable
0
R/W
When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register),
the Fatal Bus Error Interrupt is enabled. When this bit is reset, Fatal Bus Error Enable
Interrupt is disabled.
14
ERE
Early receive interrupt enable
0
R/W
When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register),
Early Receive Interrupt is enabled. When this bit is reset, Early Receive Interrupt is
disabled.
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User manual
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Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
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