MC9S12T64 Datasheet, PDF (73/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Pinout and Signal Description
Signal Descriptions
Table 13 MC9S12T64 Signal Description Summary (Continued)
Pin Function
AN7 / ETRIG
RxD0
TxD0
RxD1
TxD1
MISO
MOSI
SCK
SS
VREGEN
TEST_VPP
IOC0
IOC1
Pin Name
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Pin
Number
Description
PAD7 VDDA
66
A/D Converter channel 7, or an external trigger for the
ATD conversion
PS0
VDDX
67 SCI0 receive pin
PS1
VDDX
68 SCI0 transmit pin
PS2
VDDX
69 SCI1 receive pin
PS3
VDDX
70 SCI1 transmit pin
PS4
VDDX
71 Master in/slave out pin for serial peripheral interface
PS5
VDDX
72 Master out/slave in pin for serial peripheral interface
PS6
VDDX
73 Serial clock for serial peripheral interface system
PS7
VDDX
74
Slave select output for SPI master mode, input for slave
mode or master mode.
VREGEN VDDX
75 Internal Voltage Regulator Enable
VSSX
VDDX
VSSX
VDDX
76
5V I/O supply and Ground
77
TEST VDDX
Configures the device for various test modes including
78
SCAN testing. Also the programming voltage input for
NVMs during factory test. This pin must be tied to
ground in all applications.
PT0
VDDX
79
Capture Timer Channel
PT1
VDDX
80
MOTOROLA
Pinout and Signal Description
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MC9S12T64Revision 1.1.1
73