MC9S12T64 Datasheet, PDF (542/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Fast Background Debug Module (FBDM)
CLOCK
TARGET SYSTEM
HOST
DRIVE TO
BKGD PIN
TARGET SYSTEM
SPEEDUP
PULSE
PERCEIVED
START OF BIT TIME
BKGD PIN
HIGH-IMPEDANCE
R-C RISE
HIGH-IMPEDANCE
HIGH-IMPEDANCE
10 CYCLES
10 CYCLES
HOST SAMPLES
BKGD PIN
Figure 105 BDM Target-to-Host Serial Bit Timing (Logic 1)
EARLIEST
START OF
NEXT BIT
Figure 106 shows the host receiving a logic 0 from the target MCU.
Since the host is asynchronous to the target MCU, there is up to a one
clock-cycle delay from the host-generated falling edge on BKGD to the
start of the bit time as perceived by the target MCU. The host initiates
the bit time but the target MCU finishes it. Since the target wants the host
to receive a logic 0, it drives the BKGD pin low for 13 target clock cycles
then briefly drives it high to speed up the rising edge. The host samples
the bit level about 10 target clock cycles after starting the bit time.
MC9S12T64Revision 1.1.1
542
Fast Background Debug Module (FBDM)
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