MC9S12T64 Datasheet, PDF (391/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Enhanced Capture Timer (ECT)
Register Descriptions
16-Bit Pulse
Accumulator A
Control Register
(PACTL)
Register offset: $0060
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
Write:
PAEN
PAMOD
PEDGE
CLK1
CLK0
PAOVI
PAI
Reset:
0
0
0
0
0
0
0
0
= Reserved or unimplemented
Read or write any time.
16-Bit Pulse Accumulator A (PACA) is formed by cascading the 8-bit
pulse accumulators PAC3 and PAC2.
When PAEN is set, the PACA is enabled. The PACA shares the input pin
with IC7.
PAEN — Pulse Accumulator A System Enable
1 = Pulse Accumulator A system enabled. The two 8-bit pulse
accumulators PAC3 and PAC2 are cascaded to form the
PACA 16-bit pulse accumulator. When PACA is enabled, the
PACN3 and PACN2 registers contents are respectively the
high and low byte of the PACA.
PA3EN and PA2EN control bits in ICPAR (see page 399) have
no effect.
Pulse Accumulator Input Edge Flag (PAIF) function is enabled.
0 = 16-Bit Pulse Accumulator A system disabled. 8-bit PAC3 and
PAC2 can be enabled when their related enable bits in ICPAR
are set.
Pulse Accumulator Input Edge Flag (PAIF) function is
disabled.
PAEN is independent from TEN in TSCR1(see page 382). With timer
disabled, the pulse accumulator can still function unless pulse
accumulator is disabled.
MOTOROLA
Enhanced Capture Timer (ECT)
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MC9S12T64Revision 1.1.1
391