MC9S12T64 Datasheet, PDF (42/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Central Processing Unit (CPU)
Table 4 Instruction Set Summary (Continued)
Source Form
Operation
Address
Machine
Mode Coding (Hex)
Access Detail S X H I N Z V C
EMINM oprx0_xysppc
EMINM oprx9,xysppc
EMINM oprx16,xysppc
EMINM [D,xysppc]
EMINM [oprx16,xysppc]
Extended minimum in M; put smaller IDX
of
IDX1
2 unsigned 16-bit values in M
IDX2
MIN[(D), (M:M+1)]⇒M:M+1
[D,IDX]
N, Z, V, C bits reflect result of internal [IDX2]
compare [(D)–(M:M+1)]
18 1F xb
18 1F xb ff
18 1F xb ee ff
18 1F xb
18 1F xb ee ff
ORPW
ORPWO
OfRPWP
OfIfRPW
OfIPRPW
––––∆∆∆∆
EMUL
Extended multiply, unsigned
INH
13
ffO
(D)×(Y)⇒Y:D; 16 by 16 to 32-bit
––––∆∆–∆
EMULS
Extended multiply, signed
(D)×(Y)⇒Y:D; 16 by 16 to 32-bit
INH
18 13
OfO
––––∆∆–∆
OffO (if followed by
page 2 instruction)
EORA #opr8i
EORA opr8a
EORA opr16a
EORA oprx0_xysppc
EORA oprx9,xysppc
EORA oprx16,xysppc
EORA [D,xysppc]
EORA [oprx16,xysppc]
Exclusive OR A
(A)⊕(M)⇒A
or (A)⊕imm⇒A
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
88 ii
98 dd
B8 hh ll
A8 xb
A8 xb ff
A8 xb ee ff
A8 xb
A8 xb ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
––––∆∆0–
EORB #opr8i
EORB opr8a
EORB opr16a
EORB oprx0_xysppc
EORB oprx9,xysppc
EORB oprx16,xysppc
EORB [D,xysppc]
EORB [oprx16,xysppc]
Exclusive OR B
(B)⊕(M)⇒B
or (B)⊕imm⇒B
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
C8 ii
D8 dd
F8 hh ll
E8 xb
E8 xb ff
E8 xb ee ff
E8 xb
E8 xb ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
––––∆∆0–
ETBL oprx0_xysppc
Extended table lookup and interpolate, IDX
16-bit; (M:M+1)+
[(B)×((M+2:M+3)–(M:M+1))]⇒D
18 3F xb
ORRffffffP
––––∆∆–∆
Before executing ETBL, initialize B with fractional part of lookup value; initialize index register to point to first table entry (M:M+1). No extensions or
indirect addressing allowed.
EXG abcdxysp,abcdxysp
Exchange register contents
INH
B7 eb
P
(r1)⇔(r2) r1 and r2 same size
$00:(r1)⇒r2r1=8-bit; r2=16-bit
(r1_L)⇔(r2)r1=16-bit; r2=8-bit
––––––––
FDIV
Fractional divide; (D)÷(X)⇒X
remainder⇒D; 16 by 16-bit
INH
18 11
OffffffffffO
–––––∆∆∆
IBEQ abdxysp, rel9
Increment and branch if equal to 0
(counter)+1⇒counter
If (counter)=0, then branch
REL
(9-bit)
04 lb rr
PPP (branch)
PPO (no branch)
––––––––
IBNE abdxysp, rel9
Increment and branch if not equal to 0 REL
(counter)+1⇒counter
(9-bit)
If (counter)≠0, then branch
04 lb rr
PPP (branch)
PPO (no branch)
––––––––
IDIV
Integer divide, unsigned; (D)÷(X)⇒X INH
18 10
OffffffffffO
–––––∆0∆
Remainder⇒D; 16 by 16-bit
IDIVS
Integer divide, signed; (D)÷(X)⇒X INH
Remainder⇒D; 16 by 16-bit
18 15
OffffffffffO
––––∆∆∆∆
INC opr16a
INC oprx0_xysppc
INC oprx9,xysppc
INC oprx16,xysppc
INC [D,xysppc]
INC [oprx16,xysppc]
INCA
INCB
Increment M; (M)+1⇒M
Increment A; (A)+1⇒A
Increment B; (B)+1⇒B
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
72 hh ll
62 xb
62 xb ff
62 xb ee ff
62 xb
62 xb ee ff
42
52
rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
O
O
––––∆∆∆–
MC9S12T64Revision 1.1.1
42
Central Processing Unit (CPU)
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