MC9S12T64 Datasheet, PDF (114/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Operating Modes
MODE Register
(MODE)
Address Offset: $000B ⁽¹⁾
Bit 7
6
5
4
3
Read:
0
MODC MODB MODA
IVIS
Write:
Reset:
0
0
0
0
0
Reset:
0
0
1
0
1
Reset:
0
1
0
0
1
Reset:
0
1
1
0
1
Reset:
1
0
0
0
0
Reset:
1
0
1
0
0
Reset:
1
1
0
0
0
Reset:
1
1
1
0
0
= Unimplemented
1. Register Address = Base Address (INITRG) + Address Offset
2. PK[6:0] pins are not bonded out.
2
1
Bit 0
0
EMK⁽²⁾
EME
0
0
0
Special Single Chip
0
1
1
Emulation Exp Nar
0
0
0
Special Test
0
1
1
Emulation Exp Wide
0
0
0
Normal Single Chip
0
0
0
Normal Exp Narrow
0
0
0
Peripheral
0
0
0
Normal Exp Wide
Read: anytime (provided this register in the map)
Write: each bit has specific write conditions.
The MODE register is used to establish the operating mode and other
miscellaneous functions (i.e. internal visibility and emulation of Port E
and K).
In peripheral modes this register is not accessible but it is reset as shown
to configure system features. Changes to bits in the MODE register are
delayed one cycle after the write.
This register is not in the on-chip map in emulation and peripheral
modes.
MODC, MODB, MODA — Mode Select bits
These bits indicate the current operating mode.
MC9S12T64Revision 1.1.1
114
Operating Modes
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