MC9S12T64 Datasheet, PDF (538/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Fast Background Debug Module (FBDM)
8 BITS
SERIAL
HARDWARE IN (SI)
READ_WORD
EXAMPLE 1 _SERIAL
OUT (SO)
COMMAND
SERIAL
HARDWARE IN (SI)
READ_WORD
EXAMPLE 2 _SERIAL
OUT (SO)
COMMAND
SERIAL
HARDWARE IN (SI)
READ
(ALL OTHERS) _SERIAL
OUT (SO)
COMMAND
16 BITS
HARDWARE
DELAY
16 BITS
ADDRESS 1
ADDRESS 2
HARDWARE
DELAY
16 BITS
ADDRESS 3
DATA 1
DATA 2
ADDRESS
ADDRESS
$FFFF
DATA
DATA
NEXT
COMMAND
NEXT
COMMAND
SERIAL
HARDWARE ^{IN (SI)}
WRITE
SERIAL
OUT (SO)
COMMAND
ADDRESS
SERIAL
FIRMWARE ^{IN (SI)}
READ
SERIAL
OUT (SO)
32-TC **
DELAY
COMMAND
DATA
DATA
HARDWARE
DELAY
NEXT
COMMAND
NEXT
COMMAND
SERIAL
IN (SI)
FIRMWARE
WRITE
SERIAL
OUT (SO)
COMMAND
DATA
32-TC
DELAY
NEXT
COMMAND
GO,
TRACE,
TAGGO
SERIAL
IN (SI)
COMMAND
64-TC
DELAY
NEXT
COMMAND
SERIAL
OUT (SO)
TC = TARGET CLOCK CYCLES
HARDWARE DELAY = 8-TC if no stretch and no narrow bus.
= 21-TC stretch and or narrow bus can occur
** allow 39 target clocks if read is external with stretch and / or narrow bus
Figure 103 BDM Command Structure - SPI Mode
MC9S12T64Revision 1.1.1
538
Fast Background Debug Module (FBDM)
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