MC9S12T64 Datasheet, PDF (443/608 Pages) Motorola, Inc – Specification

Character
Reception
Data Sampling
Freescale Semiconductor, Inc.
Serial Communications Interface (SCI)
Functional Description
length of data characters. When receiving 9-bit data, bit R8 in SCI data
register high (SCIxDRH) is the ninth bit (bit 8).
During an SCI reception, the receive shift register shifts a frame in from
the RX input signal. The SCI data register is the read-only buffer
between the internal data bus and the receive shift register.
After a complete frame shifts into the receive shift register, the data
portion of the frame transfers to the SCI data register. The receive data
register full flag, RDRF, in SCI status register 1 (SCIxSR1) becomes set,
indicating that the received byte can be read. If the receive interrupt
enable bit, RIE, in SCI control register 2 (SCIxCR2) is also set, the RDRF
flag generates an RDRF interrupt request.
The receiver samples the RX input signal at the RT clock rate. The RT
clock is an internal signal with a frequency 16 times the baud rate. To
adjust for baud rate mismatch, the RT clock (see Figure 80) is
re-synchronized:
• After every start bit
• After the receiver detects a data bit change from logic 1 to logic 0
(after the majority of data bit samples at RT8, RT9, and RT10
returns a valid logic 1 and the majority of the next RT8, RT9, and
RT10 samples returns a valid logic 0)
To locate the start bit, data recovery logic does an asynchronous search
for a logic 0 preceded by three logic 1s. When the falling edge of a
possible start bit occurs, the RT clock begins to count to 16.
MOTOROLA
Serial Communications Interface (SCI)
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MC9S12T64Revision 1.1.1
443