MC9S12T64 Datasheet, PDF (356/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Pulse Width Modulator (PWM8B8C)
NOTE: Clock SB = Clock B / (2 * PWMSCLB)
When PWMSCLB = $00, PWMSCLB value is considered a full scale
value of 256. Clock B is thus divided by 512.
As an example, consider the case in which the user writes $FF into the
PWMSCLA register. Clock A for this case will be the Bus Clock divided
by 4. A pulse will occur at a rate of once every 255x4 Bus Clock cycles.
Passing this through the divide by two circuit produces a clock signal that
is the Bus Clock divided by 2040 rate. Similarly, a value of $01 in the
PWMSCLA register, when clock A is the Bus Clock divided by 4, will
produce a clock that is the Bus Clock divided by 8 rate.
Writing to PWMSCLA or PWMSCLB causes the associated 8-bit down
counter to be re-loaded. Otherwise, when changing rates the counter
would have to count down to $01 before counting at the proper rate.
Forcing the associated counter to re-load the scale register value every
time PWMSCLA or PWMSCLB is written prevents this.
CAUTION: Writing to the scale registers while channels are operating can cause
irregularities in the PWM outputs.
Clock Select
Each PWM channel has the capability of selecting one of two clocks. For
channels 0, 1, 4, and 5 the clock choices are clock A or clock SA. For
channels 2, 3, 6, and 7 the choices are clock B or clock SB. The clock
selection is done with the PCLKx control bits in the PWMCLK register.
CAUTION: Changing clock control bits while channels are operating can cause
irregularities in the PWM outputs.
PWM Channel
Timers
The main part of the PWM module are the actual timers. Each of the
timer channels has a counter, a period register and a duty register (each
are 8-bit). The waveform output period is controlled by a match between
the period register and the value in the counter. The duty is controlled by
a match between the duty register and the counter value and causes the
state of the output to change during the period. The starting polarity of
the output is also selectable on a per channel basis. Shown below in
Figure 61 is the block diagram for the PWM timer
MC9S12T64Revision 1.1.1
356
Pulse Width Modulator (PWM8B8C)
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