MC9S12T64 Datasheet, PDF (257/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Port Integration Module (PIM)
Register Descriptions
Port T Data
Direction Register
(DDRT)
Address Offset: $00E2
Bit 7
Read:
DDRT7
Write:
Reset: 0
6
5
4
DDRT6 DDRT5 DDRT4
0
0
0
= Reserved or unimplemented
3
DDRT3
0
2
DDRT2
0
1
DDRT1
0
Bit 0
DDRT0
0
Read: Anytime.
Write: Anytime.
This register configures each port T pin as either input or output.
The ECT forces the I/O state to be an output for each timer port
associated with an enabled output compare. In these cases the data
direction bits will not change.
The DDRT bits revert to controlling the I/O direction of a pin when the
associated timer output compare is disabled.
The timer input capture always monitors the state of the pin.
DDRT[7:0] — Data Direction Port T
1 = Associated pin is configured as output.
0 = Associated pin is configured as input.
Due to internal synchronization circuits, it can take up to 2 bus cycles
until the correct value is read on PTT or PTIT registers, when
changing the DDRT register.
MOTOROLA
Port Integration Module (PIM)
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MC9S12T64Revision 1.1.1
257