MC9S12T64 Datasheet, PDF (442/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Serial Communications Interface (SCI)
for a queued idle character while the TDRE flag is set and immediately
before writing the next byte to the SCI data register.
NOTE: If the TE bit is clear and the transmission is complete, the SCI is not the
master of the TxD pin.
Receiver
INTERNAL BUS
SBR12–SBR0
MODULE
CLOCK
BAUD DIVIDER
RXD
DATA
RECOVERY
FROM TXD
LOOP
CONTROL
LOOPS
RSRC
RE
RAF
M
WAKE
ILT
WAKEUP
LOGIC
PE
PARITY
PT
CHECKING
IDLE INTERRUPT REQUEST
IDLE
ILIE
RDRF/OR INTERRUPT REQUEST
RIE
SCI DATA REGISTER
11-BIT RECEIVE SHIFT REGISTER
H8 7 6 5 4 3 2 1 0 L
FE
NF
PE
R8
RDRF
OR
RWU
Figure 79 SCI Receiver Block Diagram
Receiver
The SCI receiver can accommodate either 8-bit or 9-bit data characters.
Character Length The state of the M bit in SCI control register 1 (SCIxCR1) determines the
MC9S12T64Revision 1.1.1
442
Serial Communications Interface (SCI)
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