MC9S12T64 Datasheet, PDF (462/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
Register Descriptions
This section consists of register descriptions in address order. Each
description includes a standard register diagram with an associated
figure number. Details of register bit and field function follow the register
diagrams, in bit order.
SPI Control
Register 1 (SPICR1)
Address Offset: $00D8
Read:
Write:
Reset:
Bit 7
SPIE
0
6
SPE
0
5
SPTIE
0
4
MSTR
0
3
CPOL
0
2
CPHA
1
1
SSOE
0
Bit 0
LSBFE
0
Read: anytime
Write: anytime
SPIE — SPI Interrupt Enable Bit
This bit enables SPI interrupts each time the SPIF or MODF status
flag is set.
1 = SPI interrupts enabled.
0 = SPI interrupts disabled.
SPE — SPI System Enable Bit
This bit enables the SPI system and dedicates the SPI port pins to SPI
system functions.
1 = SPI port pins are dedicated to SPI functions.
0 = SPI disabled. (lower power consumption)
SPTIE — SPI Transmit Interrupt Enable
This bit enables SPI interrupt generated each time the SPTEF flag is
set.
1 = SPTEF interrupt enabled.
0 = SPTEF interrupt disabled.
MSTR — SPI Master/Slave Mode Select Bit
MC9S12T64Revision 1.1.1
462
Serial Peripheral Interface (SPI)
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