MC9S12T64 Datasheet, PDF (108/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Operating Modes
In normal single chip mode, the MODE register is writable one time. This
allows a user program to change the bus mode to narrow or wide
expanded mode and/or turn on visibility of internal accesses.
Port E, bit 4 can be configured for a free-running E clock output by
clearing NECLK in the PEAR register. Typically, the only use for an E
clock output while the MCU is in single chip modes would be to get a
constant speed clock for use in the external application system.
Normal Expanded
Wide Mode
In expanded wide modes, Ports A and B are configured as a 16-bit
multiplexed address and data bus and Port E bit 4 is configured as the
E clock output signal. These signals allow external memory and
peripheral devices to be interfaced to the MCU.
Port E pins other than PE4/ECLK are configured as general purpose I/O
pins (initially high-impedance inputs with internal pullup resistors
enabled). Control bits PIPOE, NECLK, LSTRE, and RDWE in the PEAR
register can be used to configure Port E pins to act as bus control
outputs instead of general purpose I/O pins.
It is possible to enable the pipe status signals on Port E bits 6 and 5 by
setting the PIPOE bit in PEAR, but it would be unusual to do so in this
mode. Development systems where pipe status signals are monitored
would typically use the special variation of this mode.
The Port E bit 2 pin can be reconfigured as the R/W bus control signal
by writing “1” to the RDWE bit in PEAR. If the expanded system includes
external devices that can be written, such as RAM, the RDWE bit would
need to be set before any attempt to write to an external location. If there
are no writable resources in the external system, PE2 can be left as a
general purpose I/O pin.
The Port E bit 3 pin can be reconfigured as the LSTRB bus control signal
by writing “1” to the LSTRE bit in PEAR. The default condition of this pin
is a general purpose input because the LSTRB function is not needed in
all expanded wide applications.
The Port E bit 4 pin is initially configured as ECLK output with stretch.
The E clock output function depends upon the settings of the NECLK bit
in the PEAR register, the IVIS bit in the MODE register and the ESTR bit
MC9S12T64Revision 1.1.1
108
Operating Modes
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