MC9S12T64 Datasheet, PDF (162/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Multiplexed External Bus Interface (MEBI)
Table 30 Access Type vs. Bus Control Pins
LSTRB A0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
1
R/W
Type of Access
1
8-bit read of an even address
1
8-bit read of an odd address
0
8-bit write of an even address
0
8-bit write of an odd address
1
16-bit read of an even address
1
16-bit read of an odd address
(low/high data swapped)
0
16-bit write to an even address
0
16-bit write to an odd address
(low/high data swapped)
Stretched Bus
Cycles
In order to allow fast internal bus cycles to coexist in a system with
slower external memory resources, the HCS12 supports the concept of
stretched bus cycles (module timing reference clocks for timers and
baud rate generators are not affected by this stretching). Control bits in
the MISC register specify the amount of stretch (0, 1, 2, or 3 periods of
the internal bus-rate clock). While stretching, the CPU state machines
are all held in their current state. At this point in the CPU bus cycle, write
data would already be driven onto the data bus so the length of time write
data is valid is extended in the case of a stretched bus cycle. Read data
would not be captured by the MCU until the E clock falling edge. In the
case of a stretched bus cycle, read data is not required until the specified
setup time before the falling edge of the stretched E clock. The external
address and R/W signals remain valid during the period of stretching
(throughout the stretched E high time).
Internal Visibility
Internal visibility is available when the system is operating in expanded
wide modes, special test mode, or emulation narrow mode. It is not
available in single-chip, peripheral or normal expanded narrow modes.
Internal visibility is enabled by setting the IVIS bit in the MODE register.
If an internal access is made while E, R/W, and LSTRB are configured
as bus control outputs and internal visibility is off (IVIS=0), E will remain
low for the cycle, R/W will remain high, and address, data and the
LSTRB pins will remain at their previous state.
MC9S12T64Revision 1.1.1
162
Multiplexed External Bus Interface (MEBI)
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