MC9S12T64 Datasheet, PDF (273/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Clocks and Reset Generator (CRG)
Modes of Operation
Modes of Operation
This subsection lists and briefly describes all CRG operating modes
supported by the CRG. This is a high level description only, detailed
descriptions of operating modes are contained in later sections.
Run Mode
All functional parts of the CRG are running during Run Mode. If RTI or
COP functionality is required the individual bits of the associated rate
select registers (COPCTL, RTICTL) have to be set to a non zero value¹.
Wait Mode
Depending on the configuration of the individual bits in the CLKSEL
register this mode allows to disable the system and core clocks.
Stop Mode
Depending on the setting of the PSTP bit Stop Mode can be
differentiated between Full Stop Mode (PSTP=0) and Pseudo Stop
Mode (PSTP=1).
• Full Stop Mode
The oscillator is disabled and thus all system and core clocks are
stopped. The COP and the RTI remain frozen.
• Pseudo Stop Mode
The oscillator continues to run and most of the system and core
clocks are stopped. If the respective enable bits are set the COP
and RTI will continue to run, else they remain frozen.
Self Clock Mode
Self Clock Mode will be entered if the Clock Monitor Enable Bit (CME)
and the Self Clock Mode Enable Bit (SCME) are both asserted and the
clock monitor detects a loss of clock (external oscillator or crystal). As
soon as Self Clock Mode is entered the CRG starts to perform a clock
check. Self Clock Mode remains active until the clock check indicates
the required quality of the incoming clock signal is met (frequency and
amplitude). Self Clock Mode should be used for safety purposes only. It
MOTOROLA
1. COPCTL register is write once only
Clocks and Reset Generator (CRG)
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MC9S12T64Revision 1.1.1
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