MC9S12T64 Datasheet, PDF (454/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Serial Communications Interface (SCI)
Interrupts
Recovery from
Wait Mode
The SCI interrupt request can be used to bring the CPU out of wait
mode.
System Level
Interrupt Sources
This section describes the interrupt originated by the SCI block.The
MCU must service the interrupt requests. Table 80 lists the five interrupt
sources of the SCI. The local enables for the five SCI interrupt sources,
are described in Table 80.
Table 80 SCI Interrupt Sources
Interrupt
TDRE
Vector Address
SCI0
SCI1
TC
RDRF $FFD6, $FFD7 $FFD4, $FFD5
OR
IDLE
Source
Description
SCIxSR1[7]
SCIxSR1[6]
SCIxSR1[5]
SCIxSR1[3]
SCIxSR1[4]
Active high level detect. Indicates that a byte
was transferred from SCIxDRH/L to the
transmit shift register.
Active high level detect. Indicates that a
transmit is complete.
Active high level detects. The RDRF interrupt
indicates that received data is available in the
SCI data register.
Active high level detects. This interrupt
indicates that an overrun condition has
occurred.
Active high level detect. Indicates that
receiver input has become idle.
The SCI only originates interrupt requests. The following is a description
of how the SCI makes a request and how the MCU should acknowledge
that request. The SCI only has a single interrupt line (SCI Interrupt
signal, active high operation) and all the following interrupts, when
generated, are ORed together and issued through that port.
TDRE Description
The TDRE interrupt is set high by the SCI when the transmit shift register
receives a byte from the SCI data register. A TDRE interrupt indicates
that the transmit shift register (SCIxDRH/L) is empty and that a new byte
can be written to the SCIxDRH/L for transmission.Clear TDRE by
MC9S12T64Revision 1.1.1
454
Serial Communications Interface (SCI)
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